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ROL, ROR
Condition Codes:
X
N
Z
—
*
*
X
Not affected.
N
Set if the most significant bit of the result is set. Cleared otherwise.
Z
Set if the result is zero. Cleared otherwise.
V
Always cleared.
C
Set according to the last bit rotated out of the operand. Cleared when the
rotate count is zero.
Instruction Format (Register Rotate):
15
14
13
1
1
1
Instruction Fields (Register Rotate):
Count/Register field:
If i/r = 0, this field contains the rotate count. The values 1–7 represent counts
of 1–7, and 0 specifies a count of 8.
If i/r = 1, this field specifies a data register that contains the rotate count (mod-
ulo 64).
dr field — Specifies the direction of the rotate:
0 — Rotate right
1 — Rotate left
Size field — Specifies the size of the operation:
00 — Byte operation
01 — Word operation
10 — Long operation
i/r field — Specifies the rotate count location:
If i/r = 0, immediate rotate count
If i/r = 1, register rotate count
Register field — Specifies a data register to be rotated
Byte swapping in the low order word of a data register is best done
with ROR/ROR, W #〈8〉, Dn. A special hardware assist has been pro-
vided to minimize operation execution.
CPU32
REFERENCE MANUAL
Rotate (Without Extend)
V
C
0
*
12
11
10
9
0
COUNT/REGISTER
INSTRUCTION SET
8
7
6
5
dr
SIZE
i/r
NOTE
ROL, ROR
4
3
2
1
1
1
REGISTER
MOTOROLA
0
4-131
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