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LG is ignored during unstacking.
0 — Original operand size was byte or word
1 — Original operand size was long word
The SSW SIZ field shows operand size remaining when a fault was detected. This field
does not indicate the initial size of the operand. It also does not necessarily indicate
the proper status of a dynamically sized bus cycle. Dynamic sizing occurs on the ex-
ternal bus and is transparent to the CPU. Byte size is shown only when the original
operand was a byte. The field is reloaded into the bus controller if the RR bit is set dur-
ing unstacking. The SIZ field is encoded as follows:
00 — Long word
01 — Byte
10 — Word
11 — Unused, reserved
The function code for the faulted cycle is stacked in the FUNC field of the SSW, which
is a copy of [FC2:FC0] for the faulted bus cycle. This field is reloaded into the bus con-
troller if the RR bit is set during unstacking. All unused bits are stacked as zeros and
are ignored during unstacking. Further discussion of the SSW is included in 6.3.1
Types of Faults.
6.3.1 Types of Faults
An efficient implementation of instruction restart dictates that faults on some bus cy-
cles be treated differently than faults on other bus cycles. The CPU32 defines four fault
types: released write faults, faults during exception processing, faults during MOVEM
operand transfer, and faults on any other bus cycle.
6.3.1.1 Type I: Released Write Faults
CPU32 instruction pipelining can cause a final instruction write to overlap the execu-
tion of a following instruction. A write that is overlapped is called a released write.
Since the machine context for the instruction that queued the write is lost as soon as
the following instruction starts, it is impossible to restart the faulted instruction.
Released write faults are taken at the next instruction boundary. The stacked program
counter is that of the next unexecuted instruction. If a subsequent instruction attempts
an operand access while a released write fault is pending, the instruction is aborted
and the write fault is acknowledged. This action prevents stale data from being used
by the instruction.
The SSW for a released write fault contains the following bit pattern:
15
14
13
0
0
0
TR
TR, B1, and B0 are set if the corresponding exception is pending when the BERR ex-
ception is taken. Status regarding the faulted bus cycle is reflected in the SSW LG,
SIZ, and FUNC fields.
MOTOROLA
6-16
12
11
10
9
B1
B0
1
EXCEPTION PROCESSING
8
7
6
5
0
0
0
LG
4
3
2
SIZ
FUNC
CPU32
REFERENCE MANUAL
0
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