Motorola CPU32 Reference Manual page 316

ADD(A)
ADD(A)
ADD
AND
AND
AND
EOR
EOR
OR
OR
OR
SUB(A)
SUB(A)
SUB
CMP(A)
CMP(A)
*
CMP2 (Save)
CMP2 (Op)
MUL(S/U).W
MUL(S/U).L (Save)
MUL(S/U).L (Op)
MUL(S/U).L (Op)
DIVU.W
DIVS.W
*
DIVU.L (Save)
DIVU.L (Op)
*
DIVS.L (Save)
DIVS.L (Op)
TBL(S/U)
*
TBL(S/U) (Save)
TBL(S/U) (Op)
TBLSN
*
TBLSN (Save)
TBLSN (Op)
TBLUN
*
TBLUN (Save)
TBLUN (Op)
X = There is one bus cycle for byte and word operands and two bus cycles for long
operands. For long bus cycles, add two clocks to the tail and to the number of
cycles.
< = Maximum time; certain data or mode combinations may execute faster.
su = The execution time is identical for signed or unsigned operands.
*
These instructions have an additional save operation that other instructions do not have.
To calculate total instruction time, calculate save, 〈ea〉, and operation
execution times, then combine in the order shown, using equations in
8.1.6 Instruction Execution Time Calculation. A save operation is not run for
long word divide and multiply instructions when 〈FEA〉 = Dn,
MOTOROLA
8-16
Instruction
Rn, Rm
〈FEA〉, Rn
Dn, 〈FEA〉
Dn, Dm
〈FEA〉, Dn
Dn, 〈FEA〉
Dn, Dm
Dn, 〈FEA〉
Dn, Dm
〈FEA〉, Dn
Dn, 〈FEA〉
Rn, Rm
〈FEA〉, Rn
Dn, 〈FEA〉
Rn, Rm
〈FEA〉, Rn
〈FEA〉, Rn
〈FEA〉, Rn
〈FEA〉, Dn
〈FEA〉, Dn
*
〈FEA〉, Dl
〈FEA〉, Dn:Dl
〈FEA〉, Dn
〈FEA〉, Dn
〈FEA〉, Dn
〈FEA〉, Dn
〈FEA〉, Dn
〈FEA〉, Dn
Dn:Dm, Dp
〈CEA〉, Dn
〈CEA〉, Dn
Dn:Dm, Dp
〈CEA〉, Dn
〈CEA〉, Dn
Dn:Dm, Dp
〈CEA〉, Dn
〈CEA〉, Dn
INSTRUCTION EXECUTION TIMING
Head Tail
0 0
0 0
0 3
0 0
0 0
0 3
0 0
0 3
0 0
0 0
0 3
0 0
0 0
0 3
0 0
0 0
1 1
2 0
0 0
1 1
2 0
2 0
0 0
0 0
1 1
2 0
1 1
2 0
26 0
1 1
6 0
30 0
1 1
6 0
30 0
1 1
6 0
Cycles
2(0/1/0)
2(0/1/0)
5(0/1/x)
2(0/1/0)
2(0/1/0)
5(0/1/x)
2(0/1/0)
5(0/1/x)
2(0/1/0)
2(0/1/0)
5(0/1/x)
2(0/1/0)
2(0/1/0)
5(0/1/x)
2(0/1/0)
2(0/1/0)
3(0/1/0)
16 - 18(X/1/0)
26(0/1/0)
3(0/1/0)
46 - 52(0/1/0)
46(0/1/0)
32(0/1/0)
42(0/1/0)
3(0/1/0)
<46(0/1/0)
3(0/1/0)
<62(0/1/0)
28-30(0/2/0)
3(0/1/0)
33-35(2X/1/0)
30-34(0/2/0)
3(0/1/0)
35-39(2X/1/0)
34-40(0/2/0)
3(0/1/0)
39-45(2X/1/0)
CPU32
REFERENCE MANUAL