Exception Processing Sequence - Motorola CPU32 Reference Manual

Sources of external exception include interrupts, breakpoints, bus errors, and reset re-
quests. Interrupts are peripheral device requests for processor action. Breakpoints are
used to support development equipment. Bus error and reset are used for access con-
trol and processor restart.

6.1.3 Exception Processing Sequence

For all exceptions other than a reset exception, exception processing occurs in the fol-
lowing sequence. Refer to 6.2.1 Reset for details of reset processing.
As exception processing begins, the processor makes an internal copy of the sta-
tus register. After the copy is made, the processor state bits in the status register
are changed — the S bit is set, establishing supervisor access level, and bits T1
and T0 are cleared, disabling tracing. For reset and interrupt exceptions, the inter-
rupt priority mask is also updated.
Next, the exception number is obtained. For interrupts, the number is fetched ROM
CPU space $F (the bus cycle is an interrupt acknowledge). For all other excep-
tions, internal logic provides a vector number.
Next, current processor status is saved. An exception stack frame is created and
placed on the supervisor stack. All stack frames contain copies of the status regis-
ter and the program counter for use by RTE. The type of exception and the context
in which the exception occurs determine what other information is stored in the
stack frame.
Finally, the processor prepares to resume normal execution of instructions. The ex-
ception vector offset is determined by multiplying the vector number by four, and
the offset is added to the contents of the VBR to determine displacement into the
exception vector table. The exception vector is loaded into the program counter. If
no other exception is pending, the processor will resume normal execution at the
new address in the PC.
6.1.4 Exception Stack Frame
During exception processing, the most volatile portion of the current context is saved
on the top of the supervisor stack. This context is organized in a format called the ex-
ception stack frame.
The exception stack frame always includes the contents of status register and program
counter at the time the exception occurred. To support generic handlers, the processor
also places the vector offset in the exception stack frame and marks the frame with a
format code. The format field allows an RTE instruction to identify stack information so
that it can be properly restored.
The general form of the exception stack frame is illustrated in Figure 6-1. Although
some formats are peculiar to a particular M68000 Family processor, format 0000 is al-
ways legal and always indicates that only the first four words of a frame are present.
See 6.4 CPU32 Stack Frames for a complete discussion of exception stack frames.
CPU32
REFERENCE MANUAL
EXCEPTION PROCESSING MOTOROLA
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