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8.3.1 Fetch Effective Address
The fetch effective address table indicates the number of clock periods needed for the
processor to calculate and fetch the specified effective address. The total number of
clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are
included in the total clock cycle number. All timing data assumes two-clock reads and
writes.
Dn
An
(An)
(An)+
−(An)
(d
,An) or (d
,PC)
16
16
(xxx).W
(xxx).L
#〈data〉.B
#〈data〉.W
#〈data〉.L
(d
,An,Xn.Sz∗Sc) or (d
8
(0) (All Suppressed)
(d
)
16
(d
)
32
(An)
(Xm.Sz∗Sc)
(An,Xm.Sz∗Sc)
(d
,An) or (d
,PC)
16
16
(d
,An) or (d
,PC)
32
32
(d
,An,Xm) or (d
16
(d
,An,Xm) or (d
32
(d
,An,Xm.Sz∗Sc) or (d
16
(d
,An,Xm.Sz∗Sc) or (d
32
X = There is one bus cycle for byte and word operands and two bus cycles for long operands.
For long bus cycles, add two clocks to the tail and to the number of cycles.
NOTES:
1. The read of the effective address and replacement fetches overlap the head of the
operation by the amount specified in the tail.
2. Size and scale of the index register do not affect execution time.
3. The program counter may be substituted for the base address register An.
4. When adjusting the prefetch time for slower buses, extra clocks may be subtracted from
the head until the head reaches zero, at which time additional clocks must be added to
both the tail and cycle counts.
MOTOROLA
8-12
Instruction
,PC,Xn.Sz∗Sc)
8
,PC,Xm)
16
,PC,Xm)
32
,PC,Xm.Sz∗Sc)
16
,PC,Xm.Sz∗Sc)
32
INSTRUCTION EXECUTION TIMING
Head
Tail
Cycles
–
–
0(0/0/0)
–
–
0(0/0/0)
1
1
3(X/0/0)
1
1
3(X/0/0)
2
2
4(X/0/0)
1
3
5(X/1/0)
1
3
5(X/1/0)
1
5
7(X/2/0)
1
1
3(0/1/0)
1
1
3(0/1/0)
1
3
5(0/2/0)
4
2
8(X/1/0)
2
2
6(X/1/0)
1
3
7(X/2/0)
1
5
9(X/3/0)
1
1
5(X/1/0)
4
2
8(X/1/0)
4
2
8(X/1/0)
1
3
7(X/2/0)
1
5
9(X/3/0)
2
2
8(X/2/0)
1
3
9(X/3/0)
2
2
8(X/2/0)
1
3
9(X/3/0)
REFERENCE MANUAL
Notes
–
–
1
1
1
1,3
1
1
1
1
1
1,2,3,4
1,4
1,4
1,4
1,2,4
1,2,4
1,2,3,4
1,3,4
1,3,4
1,3,4
1,3,4
1,2,3,4
1,2,3,4
CPU32
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