Supervisor Privilege Level - Motorola CPU32 Reference Manual

formation. The operating system executes at the supervisor privilege level, has access
to all resources, performs the overhead tasks for the user level programs, and coordi-
nates their activities.

5.2.1 Supervisor Privilege Level

If the S bit in the status register is set, supervisor privilege level applies, and all instruc-
tions are executable. The bus cycles generated for instructions executed in supervisor
level are normally classified as supervisor references, and the values of the function
codes on FC[2:0] refer to supervisor address spaces.
All exception processing is performed at the supervisor level. All bus cycles generated
during exception processing are supervisor references, and all stack accesses use the
supervisor stack pointer.
Instructions that have important system effects can only be executed at supervisor lev-
el. For instance, user programs are not permitted to execute STOP, LPSTOP, or RE-
SET instructions. To prevent a user program from gaining privileged access, except in
a controlled manner, instructions that can alter the S bit in the status register are priv-
ileged. The TRAP #n instruction provides controlled user access to operating system
services.
5.2.2 User Privilege Level
If the S bit in the status register is cleared, the processor executes instructions at the
user privilege level. The bus cycles for an instruction executed at the user privilege lev-
el are classified as user references, and the values of the function codes on FC[2:0]
specify user address spaces. While the processor is at the user level, implicit referenc-
es to the system stack pointer and explicit references to address register seven (A7)
refer to the user stack pointer (USP).
5.2.3 Changing Privilege Level
To change from user privilege level to supervisor privilege level, a condition that caus-
es exception processing must occur. When exception processing begins, the current
values in the status register, including the S bit, are saved on the supervisor stack, and
then the S bit is set, enabling supervisory access. Execution continues at supervisor
level until exception processing is complete.
To return to user access level, a system routine must execute one of the following in-
structions: MOVE to SR, ANDI to SR, EORI to SR, ORI to SR, or RTE. These instruc-
tions execute only at supervisor privilege level, and can modify the S bit of the status
register. After these instructions execute, the instruction pipeline is flushed, then re-
filled from the appropriate address space.
The RTE instruction causes a return to a program that was executing when an excep-
tion occurred. When RTE is executed, the exception stack frame saved on the super-
visor stack can be restored in either of two ways.
MOTOROLA
5-2
PROCESSING STATES CPU32
REFERENCE MANUAL