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ADD
15
14
13
1
1
0
ADDA
15
14
13
1
1
0
ADDX
15
14
13
1
1
0
Size Field: 00 = Byte 01 = Word 10 = Long
R/M Field: 0 = Data Register to Data Register 1 = Memory to Memory
If R/M = 0, both registers must be data registers
If R/M = 1, both registers must be address registers for Predecrement Addressing mode
ASL, ASR (Register)
15
14
13
1
1
1
Count/Register Field:
If I/R Field = 0, Specifies Shift Count
If I/R Field = 1, Specifies Data Register that contains Shift Count
dr Field: 0 = Right 1 = Left
Size Field: 00 = Byte 01 = Word 10 = Long
I/R Field: 0 = Immediate Shift Count 1 = Register Shift Count
CPU32
REFERENCE MANUAL
12
11
10
9
1
REGISTER
Byte
Word
000
001
100
101
12
11
10
9
1
REGISTER
Word
Long
011
111
12
11
10
9
1
REGISTER Rx
12
11
10
9
0
COUNT/REGISTER
INSTRUCTION SET
8
7
6
5
OPMODE
Opmode Field:
Long
Operation
〉
) + (〈Dn
010
(〈ea
〉
) + (〈ea
110
(〈Dn
8
7
6
5
OPMODE
Opmode Field:
Operation
〉
〉
→
〉
〈An
(〈ea
) + (〈An
)
8
7
6
5
1
SIZE
0
8
7
6
5
dr
SIZE
i/r
4
3
2
1
EFFECTIVE ADDRESS
MODE
REGISTER
〉
→
〉
〈Dn
)
〉
→
〉
〈ea
)
4
3
2
1
EFFECTIVE ADDRESS
MODE
REGISTER
4
3
2
1
0
R/M
REGISTER Ry
4
3
2
1
0
0
REGISTER
MOTOROLA
0
0
0
0
4-185
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