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4.3 Instruction Summary
The instructions form a set of tools to perform the following operations:
Data movement
Integer arithmetic
Logic
Shift and rotate
The complete range of instruction capabilities combined with the addressing modes
described previously provide flexibility for program development.
4.3.1 Condition Code Register
The condition code register portion of the status register contains five bits that indicate
the result of a processor operation. Table 4-1 lists the effect of each instruction on
these bits. The carry bit and the multiprecision extend bit are separate in the M68000
Family to simplify programming techniques that use them. Refer to Table 4-5 as an
example.
Operations
ABCD
ADD, ADDI, ADDQ
ADDX
AND, ANDI, EOR, EORI,
MOVEQ, MOVE, OR,
ORI, CLR, EXT, NOT,
TAS, TST
CHK
CHK2, CMP2
SUB, SUBI, SUBQ
SUBX
CMP, CMPI, CMPM
DIVS, DIVU
MULS, MULU
SBCD, NBCD
NEG
NEGX
CPU32
REFERENCE MANUAL
Bit manipulation
Binary-coded decimal arithmetic
Program control
System control
Table 4-1 Condition Code Computations
X
N
Z
V
*
U
?
U
*
*
*
?
*
*
?
?
—
*
*
0
—
*
U
U
—
U
?
U
*
*
*
?
*
*
?
?
—
*
*
?
—
*
*
?
—
*
*
?
*
U
?
U
*
*
*
?
*
*
?
?
INSTRUCTION SET
C
Special Definition
C = Decimal Carry
?
Z = Z • Rm •... • R0
V = Sm • Dm • Rm
+
?
C = Sm • Dm; Rm • Dm
V = Sm • Dm • Rm
+
C = Sm • Dm
Rm • Dm
+
?
Z = Z • Rm •... • R0
0
U
(R = UB)
+
Z = (R = LB)
C = (LB UB) • (IR < LB)
?
(UB < LB) • (R > UB) • (R < LB)
V = Sm • Dm • Rm
+
?
C = Sm • Dm
Rm • Dm
+
V = Sm • Dm • Rm
+
C = Sm • Dm
Rm • Dm
+
?
Z = Z • Rm •... • R0
V = Sm • Dm • Rm
+
?
C = Sm • Dm
Rm • Dm
+
0
V = Division Overflow
0
V = Multiplication Overflow
C = Decimal Borrow Z =
?
Z • Rm •... • R0
V = Dm • Rm
?
+
C = Dm
Rm
V = Dm • Rm
+
?
C = Dm
Rm
Z = Z • Rm •... • R0
Sm • Dm • Rm
Sm • Rm
+
Sm • Dm • Rm
Sm • Rm
+
(R > UB)
+
+
Sm • Dm • Rm
Sm • Rm
+
Sm • Dm • Rm
Sm • Rm
+
Sm • Dm • Rm
Sm • Rm
+
MOTOROLA
4-5
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