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SBCD
Operation:
Assembler
Syntax:
Attributes:
Description:
tion operand and stores the result in the destination location. The subtraction is per-
formed using binary coded decimal arithmetic; the operands are packed BCD
numbers. The instruction has two modes:
1. Data register to data register: The data registers specified by the instruction
contain the operands.
2. Memory to memory: The address registers specified by the instruction
access the operands from memory using the predecrement addressing
mode.
Condition Codes:
X
N
Z
*
U
*
X
Set the same as the carry bit.
N
Undefined.
Z
Cleared if the result is nonzero. Unchanged otherwise.
V
Undefined.
C
Set if a borrow (decimal) is generated. Cleared otherwise.
Normally the Z condition code bit is set via programming before the
start of an operation. This allows successful tests for zero results
upon completion of multiple-precision operations.
Instruction Format:
15
14
13
1
0
0
Instruction Fields:
Register Dy/Ay field — Specifies the destination register.
If R/M = 0, specifies a data register.
If R/M = 1, specifies an address register for the predecrement addressing
mode.
R/M field — Specifies the operand addressing mode:
0 — The operation is data register to data register.
1 — The operation is memory to memory.
Register Dx/Ax field — Specifies the source register:
If R/M = 0, specifies a data register.
If R/M = 1, specifies an address register for the predecrement addressing
mode.
MOTOROLA
4-140
Subtract Decimal with Extend
Destination
– Source
10
SBCD Dx, Dy
SBCD –(Ax), –(Ay)
Size = (Byte)
Subtracts the source operand and the extend bit from the destina-
V
C
U
*
12
11
10
9
0
REGISTER Ry
INSTRUCTION SET
– X → Destination
10
NOTE
8
7
6
5
1
0
0
0
SBCD
4
3
2
1
0
R/M
REGISTER Rx
CPU32
REFERENCE MANUAL
0
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