Cpu Serial Logic - Motorola CPU32 Reference Manual

Bit 16
0
0
1
1
1
Command and data transfers initiated by the development system should clear bit 16.
The current implementation ignores this bit; however, Motorola reserves the right to
use this bit for future enhancements.

7.2.7.1 CPU Serial Logic

CPU serial logic, shown in the left-hand portion of Figure 7-5, consists of transmit and
receive shift registers and of control logic that includes synchronization, serial clock
generation circuitry, and a received bit counter.
STATUS
EXECUTION
UNIT
SYNCHRONIZE
MICROSEQUENCER
MOTOROLA
7-8
Table 7-3 CPU Generated Message Encoding
Data
xxxx Valid Data Transfer
FFFF Command Complete; Status OK
0000 Not Ready with Response; Come Again
0001 BERR Terminated Bus Cycle; Data Invalid
FFFF Illegal Command
CPU
INSTRUCTION
REGISTER BUS
16
RCV DATA LATCH
SERIAL IN
PARALLEL OUT
PARALLEL IN
SERIAL OUT
16
CONTROL
LOGIC
Figure 7-5 Debug Serial I/O Block Diagram
DEVELOPMENT SUPPORT
Message Type
DEVELOPMENT SYSTEM
0
COMMAND LATCH
DSI
PARALLEL IN
SERIAL OUT
DSO
SERIAL IN
PARALLEL OUT
RESULT LATCH
STATUS
DSCLK
CONTROL
LOGIC
REFERENCE MANUAL
DATA
16
16
DATA
SERIAL
CLOCK
CPU32