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8.3.10 Bit Manipulation Instructions
The bit manipulation instruction table indicates the number of clock periods needed for
the processor to perform the specified operation on the given addressing mode. The
total number of clock cycles is outside the parentheses. The numbers inside parenthe-
ses (r/p/w) are included in the total clock cycle number. All timing data assumes two-
clock reads and writes.
BCHG
BCHG
BCHG
BCHG
BCLR
BCLR
BCLR
BCLR
BSET
BSET
BSET
BSET
BTST
BTST
BTST
BTST
∗An # fetch effective address time must be added for this instruction:
〈FEA〉 + 〈FEA〉 + 〈OPER〉
8.3.11 Conditional Branch Instructions
The conditional branch instruction table indicates the number of clock periods needed
for the processor to perform the specified branch on the given branch size, with com-
plete execution times given. No additional tables are needed to calculate total effective
execution time for these instructions. The total number of clock cycles is outside the
parentheses. The numbers inside parentheses (r/p/w) are included in the total clock
cycle number. All timing data assumes two-clock reads and writes.
Bcc
Bcc.B
Bcc.W
Bcc.L
DBcc
DBcc
DBcc
DBcc
DBcc
DBcc
*In loop mode
MOTOROLA
8-20
Instruction
#, Dn
Dn, Dm
#, 〈FEA〉
Dn, 〈FEA〉
#, Dn
Dn, Dm
#, 〈FEA〉
Dn, 〈FEA〉
#, Dn
Dn, Dm
#, 〈FEA〉
Dn, 〈FEA〉
#, Dn
Dn, Dm
#, 〈FEA〉
Dn, 〈FEA〉
Instruction
(taken)
(not taken)
(not taken)
(not taken)
(T, not taken)
(F, −1, not taken)
(F, not −1, taken)
(T, not taken)
(F, −1, not taken)
(F, not −1, taken)
INSTRUCTION EXECUTION TIMING
Head
Tail
2
0
4
0
1
2
2
2
2
0
4
0
1
2
2
2
2
0
4
0
1
2
2
2
2
0
2
0
1
0
2
0
Head
Tail
−2
2
2
0
0
0
0
0
1
1
2
0
−2
6
4
0
6
0
6
0
Cycles
6(0/2/0)∗
6(0/1/0)
8(0/2/1)∗
8(0/1/1)
6(0/2/0)∗
6(0/1/0)
8(0/2/1)∗
8(0/1/1)
6(0/2/0)∗
6(0/1/0)
8(0/2/1)∗
8(0/1/1)
4(0/2/0)∗
4(0/1/0)
4(0/2/0)∗
8(0/1/0)
Cycles
8(0/2/0)
4(0/1/0)
4(0/2/0)
6(0/3/1)
4(0/2/0)
6(0/2/0)
10(0/2/0)
6(0/1/0)∗
8(0/1/0)∗
10(0/0/0)∗
CPU32
REFERENCE MANUAL
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