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circuit emulation. The processor remains in the target system (see Figure 7-2) and the
interface is simplified. The BSA monitors target processor operation and the on-chip
debugger controls the operating environment. Emulation is much "closer" to target
hardware, and many interfacing problems (i.e., limitations on high-frequency opera-
tion, AC and DC parametric mismatches, and restrictions on cable length) are mini-
mized.
TARGET
SYSTEM
TARGET
SYSTEM
7.1.2 Deterministic Opcode Tracking Overview
CPU32 function code outputs are augmented by two supplementary signals that mon-
itor the instruction pipeline. The instruction fetch (IFETCH) output identifies bus cycles
in which data is loaded into the pipeline, and signals pipeline flushes. The instruction
pipe (IPIPE) output indicates when each mid-instruction pipeline advance occurs and
when instruction execution begins. These signals allow a BSA to synchronize with in-
struction stream activity. Refer to 7.3 Deterministic Opcode Tracking for complete
information.
MOTOROLA
7-2
Figure 7-1 In-Circuit Emulator Configuration
TARGET
MCU
Figure 7-2 Bus State Analyzer Configuration
DEVELOPMENT SUPPORT
IN-CIRCUIT
EMULATOR
TARGET
MCU
BUS STATE
ANALYZER
CPU32
REFERENCE MANUAL
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