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3.4.3.5 Absolute Long Address
In this mode, the operand is in memory, and the address of the operand occupies the
two extension words following the instruction word in memory. The first extension word
contains the high-order part of the address; the low-order part of the address is the
second extension word.
GENERATION:
ASSEMBLER SYNTAX:
MODE:
REGISTER:
FIRST EXTENSION WORD:
SECOND EXTENSION WORD:
MEMORY ADDRESS:
NUMBER OF EXTENSION WORDS:
3.4.3.6 Immediate Data
In this addressing mode, the operand is in one or two extension words:
Byte Operation
The operand is in the low-order byte of the extension word.
Word Operation
The operand is in the extension word.
Long-Word Operation
The high-order 16 bits of the operand are in the first extension word; the low-order
16 bits are in the second extension word.
3.4.4 Effective Address Encoding Summary
Most addressing modes use one of the three formats shown in Figure 3-2. The single
EA instruction is in the format of the instruction word. The mode field of this word se-
lects the addressing mode. The register field contains the general register number or
a value that selects the addressing mode when the mode field contains "111".
Some indexed or indirect modes use the instruction word followed by the brief format
extension word. Other indexed or indirect modes consist of the instruction word and
the full format of extension words. The longest instruction for the CPU32 contains six
extension words. It is a MOVE instruction with full format extension words for both
source and destination EA and a 32-bit base displacement for both addresses.
CPU32
DATA ORGANIZATION AND ADDRESSING CAPABILITIES
REFERENCE MANUAL
EA GIVEN
(xxx).L
111
001
2
GENERATION:
ASSEMBLER SYNTAX:
MODE:
REGISTER:
NUMBER OF EXTENSION WORDS:
15
0
ADDRESS HIGH
15
31
CONCATENATION
31
OPERAND
OPERAND GIVEN
#XXX
111
100
1 OR 2
0
0
ADDRESS LOW
0
0
MOTOROLA
3-9
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