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If the frame was generated by an interrupt, breakpoint, trap, or instruction exception,
the status register and program counter are restored to the values saved on the super-
visor stack, and execution resumes at the restored program counter address, with ac-
cess level determined by the S bit of the restored status register.
If the frame was generated by a bus error or an address error exception, the entire pro-
cessor state is restored from the stack.
5.3 Types of Address Space
During each bus cycle, the processor generates function code signals that permit se-
lection of eight distinct 4-Gigabyte address spaces. Not all devices that incorporate the
CPU32 support a full complement of memory. (Refer to the appropriate user's manual
for details.) Selection varies according to the access required. Automatic selection of
supervisor and user space, and of program and data space, is provided. In addition,
certain special processor cycles, such as the interrupt acknowledge cycle or the LP-
STOP broadcast cycle are recognized, and appropriate codes are generated. Table
5-1 shows function code values and the corresponding address space.
FC2
0
0
0
0
1
1
1
1
*Address space 3 is reserved for user definition;
0 and 4 are reserved for future use by Motorola.
Although an appropriate address space is selected, memory locations of user program
and data, and of supervisor data, within that address space are not predefined. Dur-
ing reset, two long words beginning at memory location zero in the supervisor program
space are used for processor initialization. No other memory locations are explicitly
defined by the CPU32.
5.3.1 CPU Space Access
Function code $7 ([FC2:FC0] = 111) selects CPU address space. The processor com-
municates with external devices for special purposes by accessing this space. All
M68000 processors use CPU space for interrupt acknowledge cycles. The CPU32
also uses CPU space for breakpoint acknowledge and the LPSTOP broadcast.
Supervisor programs can use the MOVES instruction to access all address spaces,
including user spaces and CPU address space. Although the MOVES instruction can
be used to generate CPU space cycles, doing so may interfere with proper system op-
eration. Exercise caution when using MOVES to access CPU space.
CPU32
REFERENCE MANUAL
Table 5-1 Address Spaces
FC1
FC0
0
0
Undefined Reserved*
0
1
User Data Space
1
0
User Program Space
1
1
Undefined Reserved*
0
0
Undefined Reserved*
0
1
Supervisor Data Space
1
0
Supervisor Program Space
1
1
CPU Space
PROCESSING STATES
Address Space
MOTOROLA
5-3
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