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Mnemonic
T
F*
HI
LS
CC
CS
NE
EQ
VC
VS
PL
MI
GE
LT
GT
LE
* Not available for the Bcc instruction.
4.4 Instruction Details
The following paragraphs contain detailed information about each instruction in the
CPU32 instruction set. The instruction descriptions are arranged alphabetically by in-
struction mnemonic. Figure 4-2 shows the format of the instruction descriptions. 4.2.1
Notation applies, with the following additions.
A. The attributes line specifies the size of the operands of an instruction. When an
instruction can use operands of more than one size, a suffix is used with the
mnemonic of the instruction:
.B
.W
.L
B. In instruction set descriptions, changes in CCR bits are shown as follows:
*
—
0
1
U
CPU32
REFERENCE MANUAL
Table 4-10 Condition Tests
Condition
True
False
High
Low or Same
Carry Clear
Carry Set
Not Equal
Equal
Overflow Clear
Overflow Set
Plus
Minus
Greater or Equal
Less Than
Greater Than
Less or Equal
Byte
Word
Long word
Set according to result of operation
Not affected by operation
Cleared
Set
Undefined after operation
INSTRUCTION SET
Encoding
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
N • V
1100
N • V
1101
N • V • Z
1110
Z; N • V; N • V
1111
Test
1
0
C • Z
+
C
Z
C
C
Z
Z
V
V
N
N
N • V
+
N • V
+
N • V • Z
+
MOTOROLA
4-13
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