Motorola CPU32 Reference Manual page 7

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7.2.4 Command Execution .........................................................................7-5
7.2.5 Background Mode Registers ............................................................. 7-6
7.2.5.1 Fault Address Register (FAR) ................................................... 7-6
7.2.5.2 Return Program Counter (RPC) ................................................ 7-6
7.2.5.3 Current Instruction Program Counter (PCC) ............................. 7-7
7.2.6 Returning from BDM .......................................................................... 7-7
7.2.7 Serial Interface ..................................................................................7-7
7.2.7.1 CPU Serial Logic ....................................................................... 7-8
7.2.7.2 Development System Serial Logic .......................................... 7-10
7.2.8 Command Set .................................................................................7-11
7.2.8.1 Command Format ................................................................... 7-11
7.2.8.2 Command Sequence Diagram ................................................ 7-12
7.2.8.3 Command Set Summary ......................................................... 7-14
7.2.8.4 Read A/D Register (RAREG/RDREG) .................................... 7-15
7.2.8.5 Write A/D Register (WAREG/WDREG) ................................... 7-15
7.2.8.6 Read System Register (RSREG) ............................................ 7-16
7.2.8.7 Write System Register (WSREG) ...........................................7-16
7.2.8.8 Read Memory Location (READ) .............................................. 7-17
7.2.8.9 Write Memory Location (WRITE) ............................................ 7-18
7.2.8.10 Dump Memory Block (DUMP) ................................................. 7-19
7.2.8.11 Fill Memory Block (FILL) ......................................................... 7-21
7.2.8.12 Resume Execution (GO) ......................................................... 7-22
7.2.8.13 Call User Code (CALL) ........................................................... 7-22
7.2.8.14 Reset Peripherals (RST) ......................................................... 7-24
7.2.8.15 No Operation (NOP) ................................................................ 7-24
7.2.8.16 Future Commands .................................................................. 7-25
7.3 Deterministic Opcode Tracking ............................................................... 7-25
7.3.1 Instruction Fetch (IFETCH) .............................................................7-25
7.3.2 Instruction Pipe (IPIPE) ................................................................... 7-25
7.3.3 Opcode Tracking during Loop Mode ............................................... 7-27
8.1 Resource Scheduling ................................................................................ 8-1
8.1.1 Microsequencer ................................................................................. 8-1
8.1.2 Instruction Pipeline ............................................................................ 8-2
8.1.3 Bus Controller Resources ................................................................. 8-2
8.1.3.1 Prefetch Controller .................................................................... 8-3
8.1.3.2 Write-Pending Buffer ................................................................. 8-3
8.1.3.3 Microbus Controller ................................................................... 8-3
8.1.4 Instruction Execution Overlap ........................................................... 8-4
CPU32
REFERENCE MANUAL
TABLE OF CONTENTS
(Continued)
Title
SECTION 8
INSTRUCTION EXECUTION TIMING
Page
MOTOROLA
vii