Return From Exception - Motorola CPU32 Reference Manual

Exception processing occurs as follows. First, the processor makes an internal copy
of the status register. After the copy is made, the processor state bits in the status reg-
ister are changed — the S bit is set, establishing supervisor access level, and bits T1
and T0 are cleared, disabling tracing. Then, priority level is set to the level of the inter-
rupt and the processor fetches a vector number from the interrupting device (CPU
space $F). The fetch bus cycle is classified as an interrupt acknowledge and the en-
coded level number of the interrupt is placed on the address bus.
If an interrupting device requests automatic vectoring, the processor generates a vec-
tor number (25 to 31) determined by the interrupt level number.
If the response to the interrupt acknowledge bus cycle is a bus error, the interrupt is
taken to be spurious, and the spurious interrupt vector number (24) is generated.
The exception vector number, program counter, and status register are saved on the
supervisor stack. The saved value of the program counter is the address of the instruc-
tion that would have executed if the interrupt had not occurred.
Priority level seven interrupt is a special case. Level seven interrupts are nonmaskable
interrupts (NMI). Level seven requests are transition sensitive to eliminate redundant
servicing and concomitant stack overflow. Transition sensitive means that the level
seven input must change state before the CPU will detect an interrupt.
An NMI is generated each time the interrupt request level changes to level seven (re-
gardless of priority mask value), and each time the priority mask changes from seven
to a lower number while request level remains at seven.
Many M68000 peripherals provide for programmable interrupt vector numbers to be
used in the system interrupt request/acknowledge mechanism. If the vector number is
not initialized after reset and if the peripheral must acknowledge an interrupt request,
the peripheral should return the uninitialized interrupt vector number (15).
See the system integration user's manual for detailed information on interrupt ac-
knowledge cycles.

6.2.12 Return from Exception

When exception stacking operations for all pending exceptions are complete, the pro-
cessor begins execution of the handler for the last exception processed. After the ex-
ception handler has executed, the processor must restore the system context in
existence prior to the exception. The RTE instruction is designed to accomplish this
task.
When RTE is executed, the processor examines the stack frame on top of the super-
visor stack to determine if it is valid and determines what type of context restoration
must be performed. See 6.4 CPU32 Stack Frames for a description of stack frames.
For a normal four-word frame, the processor updates the status register and program
counter with data pulled from the stack, increments the supervisor stack pointer by
eight, and resumes normal instruction execution. For a six-word frame, the status reg-
CPU32
REFERENCE MANUAL
EXCEPTION PROCESSING MOTOROLA
6-13