State Transitions - Motorola CPU32 Reference Manual

This section describes the processing states of the CPU32. It includes a functional de-
scription of the bits in the supervisor portion of the status register and an overview of
actions taken by the processor in response to exception conditions.

5.1 State Transitions

The processor is in normal, background, or exception state unless halted.
When the processor fetches instructions and operands or executes instructions, it is
in the normal processing state. The stopped condition, which the processor enters
when a STOP or LPSTOP instruction is executed, is a variation of the normal state in
which no further bus cycles are generated.
Background state is an alternate operational mode used for system debugging. Refer
to SECTION 7 DEVELOPMENT SUPPORT for more information.
Exception processing refers specifically to the transition from normal processing of a
program to normal processing of system routines, interrupt routines, and other excep-
tion handlers. Exception processing includes the stack operations, the exception vec-
tor fetch, and the filling of the instruction pipeline caused by an exception. Exception
processing ends when execution of an exception handler routine begins. Refer to
SECTION 6 EXCEPTION PROCESSING for comprehensive information.
A catastrophic system failure occurs if the processor detects a bus error or generates
an address error while in the exception processing state. This type of failure halts the
processor. For example, if a bus error occurs during exception processing caused by
a bus error, the CPU32 assumes that the system is not operational and halts.
The halted condition should not be confused with the stopped condition. After the pro-
cessor executes a STOP or LPSTOP instruction, execution of instructions can resume
when a trace, interrupt, or reset exception occurs.
5.2 Privilege Levels
To protect system resources, the processor can operate with either of two levels of ac-
cess — user or supervisor. Supervisor level is more privileged than user level. All in-
structions are available at the supervisor level, but execution of some instructions is
not permitted at the user level. There are separate stack pointers for each level. The
S bit in the status register indicates privilege level, and determines which stack pointer
is used for stack operations. The processor identifies each bus access (supervisor or
user mode) via function codes to enforce supervisor and user access levels.
In a typical system most programs execute at the user level. User programs can ac-
cess only their own code and data areas, and are restricted from accessing other in-
CPU32
REFERENCE MANUAL
SECTION 5
PROCESSING STATES
PROCESSING STATES MOTOROLA
5-1