Save And Restore Operations - Motorola CPU32 Reference Manual

BKPT (Acknowledged)
BKPT (Bus Error)
Breakpoint (Acknowledged)
Breakpoint (Bus Error)
Interrupt
RESET
STOP
LPSTOP
Divide-by-Zero
Trace
TRAP #
ILLEGAL
A-line
F-line (First word illegal)
F-line (Second word illegal) ea = Rn
F-line (Second word illegal) ea ≠ Rn (Save)
F-line (Second word illegal) ea ≠ Rn (Op)
Privileged
TRAPcc (trap)
TRAPcc (no trap)
TRAPcc.W (trap)
TRAPcc.W (no trap)
TRAPcc.L (trap)
TRAPcc.L (no trap)
TRAPV (trap)
TRAPV (no trap)
∗Minimum interrupt acknowledge cycle time is assumed to be three clocks.
NOTE: The F-line (Second word illegal) operation involves a save step which other
operations do not have. To calculate, total the operation time, calculate the Save,
then calculate effective address and the Operation execution times. Combine in
the order listed, using the equations given in 8.1.6 Instruction Execution Time Calculation.

8.3.14 Save and Restore Operations

The save and restore operations table indicates the number of clock periods needed
for the processor to perform the specified state save or return from exception. Com-
plete execution times and stack length are given. No additional tables are needed to
calculate total effective execution time for these instructions. The total number of clock
cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are includ-
ed in the total clock cycle number. All timing data assumes two-clock reads and writes.
BERR on instruction
BERR on exception
RTE (four-word frame)
RTE (six-word frame)
RTE (BERR on instruction)
RTE (BERR on four-word frame)
RTE (BERR on six-word frame)
< = Maximum time is indicated — certain data or mode combinations execute faster.
Y = If a bus error occurred during a write cycle, the cycle is rerun by the RTE.
MOTOROLA
8-22
Instruction
Instruction
INSTRUCTION EXECUTION TIMING
Head Tail
0 0
−2
0
0 0
−2
0
−2
0
0 0
2 0
−2
3
−2
0
−2
0
−2
4
−2
0
−2
0
−2
0
−2
1
1 1
4 -2
−2
0
−2
2
2 0
−2
2
0 0
−2
0
0 0
−2
2
2 0
Head Tail
−2
0
−2
0
−2
1
−2
1
−2
1
−2
1
−2
1
Cycles
14(1/0/0)
35(3/2/4)
10(1/0/0)
42(3/2/6)
30(3/2/4)∗
518(0/1/0)
12(0/1/0)
25(0/3/1)
36(2/2/6)
36(2/2/6)
29(2/2/4)
25(2/2/4)
25(2/2/4)
25(2/2/4)
31(2/3/4)
3(0/1/0)
29(2/2/4)
25(2/2/4)
38(2/2/6)
4(0/1/0)
38(2/2/6)
4(0/2/0)
38(2/2/6)
6(0/3/0)
38(2/2/6)
4(0/1/0)
Cycles
<58(2/2/12)
48(2/2/12)
24(4/2/0)
26(4/2/0)
50(12/12/Y)
66(10/2/4)
70(12/2/6)
CPU32
REFERENCE MANUAL