Type 0000 — Breakpoint - Motorola CPU32 Reference Manual

Address bus encoding facilitates CPU space transactions. Bits A[19:16], the CPU
space type field, show which transaction is being performed. Currently, only five of the
16 possible encodings are defined: 0000, 0001, 0010, 0011, and 1111. Of these, only
0000, 0011, and 1111 are supported by the CPU32.
Address bits A[31:20] are not present on all M68000 processors, and thus cannot be
essential to CPU space transaction decoding. The function of other address bus bit
fields depends on the transaction being performed. A description of each defined CPU
space types follows.
5.3.1.1 Type 0000 — Breakpoint
This CPU space type is used for breakpoint acknowledge.
31
0 0 0 0 0 0 0 0
BKPT# field A[4:2] indicates the breakpoint number. Software breakpoints set this val-
ue to the number of the executing breakpoint instruction. Hardware breakpoints al-
ways set BKPT# to 7 (%111).
T bit A1 designates the type of breakpoint. T = 0 indicates a software breakpoint; T =
1 indicates a hardware breakpoint.
5.3.1.2 Type 0001 — MMU Access
This type of access is not supported by the CPU32 processor. This space is reserved
for future use.
5.3.1.3 Type 0010 — Coprocessor Access
This type of access is not supported by the CPU32 processor. This space is reserved
for future use.
5.3.1.4 Type 0011 — Internal Register Access
Type 0011 space is used to access certain critical system configuration or control reg-
isters.
The CPU32 external bus interface interrupt mask register resides in CPU space. This
register is written to when LPSTOP is executed, and masks off external interrupts
while in stop mode. A[3:1] indicate the encoded interrupt mask level.
31
0 0 0 0 0 0 0 0
MOTOROLA
5-4
0 0 0 0 0 0 0 0
18 17
0 0 0 0 0 0 1 1
DATA
PROCESSING STATES
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0
15
5 4 2
0 0 0 BKPT #
1 1 1 BKPT #
0 0 0 0 0 1
3 2
CPU32
REFERENCE MANUAL
1 0
T 0
1 0
T 0
1 0
1 0