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DIVU
DIVUL
Operation:
Assembler
Syntax:
Attributes:
Description:
operand and stores the unsigned result in the destination. The instruction uses one of
four forms.
The word form of the instruction divides a long word by a word. The result is a
quotient in the lower word (least significant 16 bits) and a remainder in the upper
word (most significant 16 bits) of the destination.
The first long form divides a long word by a long word. The result is a long quo-
tient; the remainder is discarded.
The second long form divides a quad word (in any two data registers) by a long
word. The result is a long word quotient and a long word remainder.
The third long form divides a long word by a long word. The result is a long word
quotient and a long word remainder.
Two special conditions may arise during the operation:
1. Division by zero causes a trap.
2. Overflow may be detected before instruction completion. If an overflow is
detected, the overflow condition code is set and the operands are unaffected.
Condition Codes:
X
N
Z
—
*
*
X
Not affected.
N
Set if quotient is negative. Cleared otherwise. Undefined if overflow or divide
by zero occurs.
Z
Set if quotient is zero. Cleared otherwise. Undefined if overflow or divide by
zero occurs.
V
Set if division overflow occurs; undefined if divide by zero occurs. Cleared oth-
erwise.
C
Always cleared.
CPU32
REFERENCE MANUAL
Unsigned Divide
Destination/Source → Destination
DIVS.W 〈ea〉, Dn32/16 → 16r:16q
DIVS.L 〈ea〉, Dq32/32 → 32q
DIVS.L 〈ea〉, Dr:Dq64/32 → 32r:32q
DIVSL.L 〈ea〉, Dr:Dq32/32 →32r:32q
Size = (Word, Long)
Divides the unsigned destination operand by the unsigned source
V
C
*
0
INSTRUCTION SET
DIVU
DIVUL
MOTOROLA
4-69
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