Table Example 5: Surface Interpolations - Motorola CPU32 Reference Manual

4.6.5 Table Example 5: Surface Interpolations

The various forms of table can be used to perform surface (3D) TLIs. However, since
the calculation must be split into a series of 2D TLIs, the possibility of losing precision
in the intermediate results is possible. The following code sequence, incorporating
both TBLS and TBLSN, eliminates this possibility.
L0:
MOVE.W
TBLSN.B
TBLSN.B
TBLS.W
ASR.L
BCC.B
ADDQ.B
L1: . . .
Before execution of this code sequence, Dx must contain fraction and entry numbers
for the two TLI, and Dm must contain the fraction for surface interpolation. The 〈ea〉
fields in the TBLSN instructions point to consecutive columns in a 3D table. The TBLS
size parameter must be word if the TBLSN size parameter is byte, and must be long
word if TBLSN is word. Increased size is necessary because a larger number of sig-
nificant digits is needed to accommodate the scaled fractional results of the 2D TLI.
4.7 Nested Subroutine Calls
The LINK instruction pushes an address onto the stack, saves the stack address at
which the address is stored, and reserves an area of the stack for use. Using this in-
struction in a series of subroutine calls will generate a linked list of stack frames.
The UNLK instruction removes a stack frame from the end of the list by loading an ad-
dress into the stack pointer and pulling the value at that address from the stack. When
the instruction operand is the address of the link address at the bottom of a stack
frame, the effect is to remove the stack frame from both the stack and the linked list.
4.8 Pipeline Synchronization with the NOP Instruction
Although the no operation (NOP) instruction performs no visible operation, it does
force synchronization of the instruction pipeline, since all previous instructions must
complete execution before the NOP begins.
MOTOROLA
4-194
Dx, Dl Copy entry number and fraction number
〈ea〉, Dx
〈ea〉, Dl
Dx:Dl, Dm Surface interpolation, with round
#8, Dm Read just the result
L1 No round necessary
#1, Dl Half round up
INSTRUCTION SET CPU32
REFERENCE MANUAL