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Frequency Counter
Frequency Counter
The frequency counter counts the frequency of the last IF and provides
accurate timing signals for digital zero-spans. The circuit also provides
timing signals to the ADC (analog to digital converter) on the A3
interface assembly. The nominal input frequency is 5.35 MHz
(10.7 MHz divided by 2). The 10 MHz reference from the A15 RF
assembly provides the frequency reference in the frequency count mode.
The frequency reference in digitized zero spans (sweep times ≥30 ms) is
the 4 MHz HPIB_CLK, selected by a clock select multiplexer in U35.
The 10 MHz reference from the A15 RF assembly is first filtered and
passed through a comparator to generate a TTL, 50 percent duty cycle
signal. C128, L16, and R91 provide a bandpass filter centered at
10 MHz. The output of comparator U33B is the actual reference used
for the Frequency Counter. An additional stage of filtering is performed
on this signal to provide a 10 MHz signal for the A17 LCD Driver
assembly.
In the frequency count mode, the 10 MHz reference is prescaled by 5 to
generate a 2 MHz timebase. This timebase feeds through the clock
select multiplexer in U35 to the CLK2 input of programmable timer
U15. The output (OUT2) of programmable timer U15 is the gating
signal (HBKT_PULSE); it performs the frequency count. The gating
time interval is a function of the counter resolution which may be set
between 10 Hz and 1 MHz.
Table 10-1 on page 506
lists the gate time
for each setting of COUNTER RES. The gate time is the period during
which HBKT_PULSE (pin 20 of U15) is low.
The FREQ COUNT input, A2J13, is gated by HBKT_PULSE. The
gated signal clocks divide-by-16 counters within U35. These counters
are cascaded to form a divide-by-256 counter. The MSB of this counter,
CD7, clocks the CLK0 input of U15. The frequency of CD7 is a function
of COUNTER RES as shown in
Table 10-1 on page
506. If timer U15
overflows, OUT0 will be set, generating CNTOVFLIRQ, which will
interrupt the CPU.
If IRQAK2 is high, HBKT_PULSE will generate FREQCNTLIRQ.
Upon receiving the FREQCNTLIRQ interrupt, the CPU latches the
CD0 to CD7 onto the BID bus by setting LCDRD (low counter data
read) low and reading the counter data from the BID bus. The CPU will
also read the data from the timer, U15, by setting L8254CS and
LCNTLRD low, placing the timer data on the BID bus. The CPU then
resets IRQAK2 low.
Chapter 10
505
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