Figure 244. Rxne Behavior In Receive-Only Mode (Bidirmode=0 And Rxonly=1) In The Case Of - ST STM32F101xx Reference Manual

RM0008

Figure 244. RXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1) in the case of

continuous transfers
Example with CPOL=1, CPHA=1, RXONLY=1
SCK
MISO/MOSI (in)
RXNE flag
Rx buffer
(read from SPI_DR)
Bidirectional receive procedure (BIDIMODE=1 and BIDIOE=0)
In this mode, the procedure is similar to the Receive-only mode procedure except that the
BIDIMODE bit has to be set and the BIDIOE bit cleared in the SPI_CR2 register before
enabling the SPI.
Continuous and discontinuous transfers
When transmitting data in master mode, if the software is fast enough to detect each rising
edge of TXE (or TXE interrupt) and to immediately write to the SPI_DR register before the
ongoing data transfer is complete, the communication is said to be continuous. In this case,
there is no discontinuity in the generation of the SPI clock between each data item and the
BSY bit is never cleared between each data transfer.
On the contrary, if the software is not fast enough, this can lead to some discontinuities in
the communication. In this case, the BSY bit is cleared between each data transmission
(see Figure
In Master receive-only mode (RXONLY=1), the communication is always continuous and the
BSY flag is always read at 1.
In slave mode, the continuity of the communication is decided by the SPI master device. In
any case, even if the communication is continuous, the BSY flag goes low between each
transfer for a minimum duration of one SPI clock cycle (see
DATA 1 = 0xA1
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
set by hardware
software waits until RXNE=1
and reads 0xA1 from SPI_DR
245).
Doc ID 13902 Rev 12
DATA 2 = 0xA2
cleared by software
0xA1
software waits until RXNE=1
and reads 0xA2 from SPI_DR
Serial peripheral interface (SPI)
DATA 3 = 0xA3
0xA2
software waits until RXNE=1
and reads 0xA3 from SPI_DR
Figure 243).
0xA3
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