ST STM32F101xx Reference Manual page 1043

RM0008
Table 214. Ethernet register map and reset values (continued)
Offset Register
ETH_MACA3
AE SA
HR
0x58
Reset value 0 0
ETH_MACA3
LR
0x5C
Reset value 1 1
ETH_MMCCR
0x100
Reset value
ETH_MMCRI
R
0x104
Reset value
ETH_MMCTI
R
0x108
Reset value
ETH_MMCRI
MR
0x10C
Reset value
ETH_MMCTI
MR
0x110
Reset value
ETH_MMCTG
FSCCR
0x14C
Reset value 0 0
ETH_MMCTG
FMSCCR
0x150
Reset value 0 0
ETH_MMCTG
FCR
0x168
Reset value 0 0
ETH_MMCRF
CECR
0x194
Reset value 0 0
ETH_MMCRF
0x198 AECR
Reset value 0 0
ETH_MMCR
GUFCR
0x1C4
Reset value 0 0
ETH_PTPTS
CR
0x700
Reset value
ETH_PTPSSI
R
0x704
Reset value
ETH_PTPTS
HR
0x708
Reset value 0 0
ETH_PTPTSL
R
0x70C
Reset value 0 0
ETH_PTPTS
HUR
0x710
Reset value 0 0
ETH_PTPTSL
UR
0x714
Reset value 0 0
Ethernet (ETH): media access control (MAC) with DMA controller
MBC
0 0 0 0 0 0
1 1 1 1 1 1 1 1
Reserved
Reserved
Reserved
Reserved
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Doc ID 13902 Rev 12
Reserved
1 1
MACA3L
1 1 1 1 1 1 1 1
Reserved
0
Reserved
0 0 0
0
Reserved
0 0 0
TGFSCC
0 0 0 0 0 0 0 0
TGFMSCC
0 0 0 0 0 0 0 0
TGFC
0 0 0 0 0 0 0 0
RFCEC
0 0 0 0 0 0 0 0
RFAEC
0 0 0 0 0 0 0 0
RGUFC
0 0 0 0 0 0 0 0
Reserved
Reserved
STS[31:0]
0 0 0 0 0 0 0 0
STSS
0 0 0 0 0 0 0 0
TSUS
0 0 0 0 0 0 0 0
TSUSS
0 0 0 0 0 0 0 0
MACA3H
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
Reserved
0
Reserved
Reserved
0
Reserved
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1
1 1 1 1 1 1
0 0 0 0
Reserved
0
Reserved
0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
STSSI
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
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