ST STM32F101xx Reference Manual page 1071

Advanced arm-based 32-bit mcus

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Debug support (DBG)

Bit 0 DBG_SLEEP: Debug Sleep mode

0: (FCLK=On, HCLK=Off) In Sleep mode, FCLK is clocked by the system clock as previously

configured by the software while HCLK is disabled.

In Sleep mode, the clock controller configuration is not reset and remains in the previously

programmed state. Consequently, when exiting from Sleep mode, the software does not

need to reconfigure the clock controller.

1: (FCLK=On, HCLK=On) In this case, when entering Sleep mode, HCLK is fed by the same

clock that is provided to FCLK (system clock as previously configured by the software).

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