Table of Contents
Advertisement
RM0008
The Hash table high register contains the higher 32 bits of the multicast Hash table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 HTH: Hash table high
This field contains the upper 32 bits of Hash table.
Ethernet MAC hash table low register (ETH_MACHTLR)
Address offset: 0x000C
Reset value: 0x0000 0000
The Hash table low register contains the lower 32 bits of the multi-cast Hash table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 HTL: Hash table low
This field contains the lower 32 bits of the Hash table.
Ethernet MAC MII address register (ETH_MACMIIAR)
Address offset: 0x0010
Reset value: 0x0000 0000
The MII address register controls the management cycles to the external PHY through the
management interface.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:16 Reserved
Bits 15:11 PA: PHY address
This field tells which of the 32 possible PHY devices are being accessed.
Bits 10:6 MR: MII register
These bits select the desired MII register in the selected PHY device.
Bit 5 Reserved
Ethernet (ETH): media access control (MAC) with DMA controller
Reserved
Doc ID 13902 Rev 12
HTH
HTL
PA
rw rw rw rw rw rw rw rw rw rw
9
8
7
6
5
4
3
9
8
7
6
5
4
3
9
8
7
6
5
4
3
MR
CR
rw rw rw
2
1
0
2
1
0
2
1
0
MW MB
rc_
rw
w1
1007/1096
Advertisement
Table of Contents
