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Ethernet (ETH): media access control (MAC) with DMA controller
Bits 15:0 MACA1H: MAC address1 high [47:32]
This field contains the upper 16 bits (47:32) of the 6-byte second MAC address.
Ethernet MAC address1 low register (ETH_MACA1LR)
Address offset: 0x004C
Reset value: 0xFFFF FFFF
The MAC address 1 low register holds the lower 32 bits of the 6-byte second MAC address
of the station.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 MACA1L: MAC address1 low [31:0]
This field contains the lower 32 bits of the 6-byte MAC address1. The content of this field is
undefined until loaded by the application after the initialization process.
Ethernet MAC address 2 high register (ETH_MACA2HR)
Address offset: 0x0050
Reset value: 0x0000 FFFF
The MAC address 2 high register holds the upper 16 bits of the 6-byte second MAC address
of the station.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
AE SA
MBC
rw rw rw rw rw rw rw rw
AE: Address enable
Bit 31
When this bit is set, the address filters use the MAC address2 for perfect filtering. When reset,
the address filters ignore the address for filtering.
SA: Source address
When this bit is set, the MAC address 2 [47:0] is used for comparison with the SA fields of the
Bit 30
received frame.
When this bit is reset, the MAC address 2 [47:0] is used for comparison with the DA fields of
the received frame.
MBC: Mask byte control
These bits are mask control bits for comparison of each of the MAC address2 bytes. When set
high, the MAC core does not compare the corresponding byte of received DA/SA with the
contents of the MAC address 2 registers. Each bit controls the masking of the bytes as follows:
– Bit 29: ETH_MACA2HR [15:8]
Bits 29:24
– Bit 28: ETH_MACA2HR [7:0]
– Bit 27: ETH_MACA2LR [31:24]
...
– Bit 24: ETH_MACA2LR [7:0]
1016/1096
MACA1L
Reserved
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Doc ID 13902 Rev 12
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MACA2H
RM0008
2
1
0
2
1
0
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