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RM0008
Table 232. Document revision history (continued)
Date
Revision
11-Feb-2009
8
Reset value corrected in
Section 11.10: Temperature sensor
ADC watchdog high threshold register
Section 12.3.9: Triangle-wave generation
updated.
Section 24.6: STM32F10xxx in Debug mode
register (CAN_MCR) on page
Note added to
Section 25.3.6: CRC
Changes concerning the I
– In
Slave transmitter on page
diagram for slave transmitter
– In
Slave receiver on page
for slave receiver
modified.
–
Master transmitter on page 734
– In
Closing the communication on page
sequence diagram for master transmitter
–
Figure 273: Method 1: transfer sequence diagram for master receiver
–
Overrun/underrun error (OVR) on page 740
–
Section 26.3.7: DMA requests
– In
Section 26.6.1: Control register 1
modified under POS bit.
– Receiver mode modified in DR bit description in
– Note added to TxE and RxNE bit descriptions in
(I2C_SR1).
Changes in FSMC section:
– Data setup and Address hold min values corrected in
NOR/PSRAM access
– Memory wait min value corrected in
parameters.
– Bit descriptions modified in
(FSMC_BTR1..4) on page
– DATAST and ADDHLD are reserved when equal to 0x0000 in
select timing registers 1..4 (FSMC_BTR1..4) on page 523
timing registers 1..4 (FSMC_BWTR1..4) on page
– Bit descriptions modified in
(FSMC_PMEM2..4)
– ATTHOLDx and ATTWAITx bit descriptions modified in
registers 2..4 (FSMC_PATT2..4)
– IOHOLDx bit description modified in
Doc ID 13902 Rev 12
Changes
Section 4.4.1: Data register
modified. Reset value corrected in
(ADC_HTR).
and
Figure 46: DAC triangle wave generation
added. Bit 16 updated in
650.
calculation.
2
C peripheral
(Inter-integrated circuit (I2C)
730: text changes and
modified.
731: text changes and
and
Master receiver on page 735
734: text changes and
modified.
clarified.
and
Section 26.3.8: Packet error checking
(I2C_CR1): note modified under STOP bit and notes
parameters.
Table 128: Programmable NAND/PC Card access
SRAM/NOR-Flash chip-select timing registers 1..4
523.
Common memory space timing register 2..4
I/O space timing register 4 (FSMC_PIO4)
Revision history
(CRC_DR).
Section 11.12.7:
CAN master control
interface):
Figure 270: Transfer sequence
Figure 271: Transfer sequence diagram
clarified.
Figure 272: Transfer
modified.
Section 26.6.5: Data register
Section 26.6.6: Status register 1
Table 103: Programmable
SRAM/NOR-Flash chip-
and
SRAM/NOR-Flash write
525.
Attribute memory space timing
updated.
(I2C_DR).
1087/1096
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