ST STM32F101xx Reference Manual page 1083

RM0008
Table 232. Document revision history (continued)
Date Revision
22-May-2008 4
continued continued
In Section 7: Low-, medium-, high- and XL-density reset and clock control (RCC) on
page 87:
– LSI calibration on page 93
– Figure 7: Simplified diagram of the reset circuit on page 88
– APB2 peripheral reset register (RCC_APB2RSTR) on page 103
– APB1 peripheral reset register (RCC_APB1RSTR) on page 106
– AHB peripheral clock enable register (RCC_AHBENR)
– APB2 peripheral clock enable register (RCC_APB2ENR)
– APB1 peripheral clock enable register (RCC_APB1ENR) on page 111
Section Table 18.: RCC register map and reset
– LSERDYIE definition modified in
– HSITRIM[4:0] definition modified in
In Section 9: General-purpose and alternate-function I/Os (GPIOs and AFIOs) on
page 154:
– GPIO ports F and G added
– In Section 9.3: Alternate function I/O and debug configuration (AFIO) on page 169
remapping for High-density devices added, note modified under
Section 9.3.3 on page 170
– AF remap and debug I/O configuration register (AFIO_MAPR)
Updated in Section 10: Interrupts and events on page
– number of maskable interrupt channels
– number of GPIOs (see
In Section 13: DMA controller (DMA) on page
– number of DMA controllers and configurable DMA channels updated
– Figure 48: DMA block diagram in connectivity line devices on page 264
added
– Note updated in Section 13.3.2: Arbiter on page 266
– Note updated in Section 13.3.6: Interrupts on page 269
– Figure 50: DMA1 request mapping on page 270
– DMA2 controller on page 271
In Section 11: Analog-to-digital converter (ADC) on page
– ADC3 added (Figure 22: Single ADC block diagram on page 207
External trigger for injected channels for ADC3
Section 12: Digital-to-analog converter (DAC) on page 243
In Section 14: Advanced-control timers (TIM1&TIM8) on page
– Advanced control timer TIM8 added (see
diagram on page 282)
– TS[2:0] modified in Section 14.4.3: TIM1&TIM8 slave mode control register
(TIMx_SMCR) on page
In Section 15: General-purpose timers (TIM2 to TIM5) on page
– TIM5 added
– Figure 100: General-purpose timer block diagram
trigger connection on page 388
RTC clock sources specified in
Section 18.1: RTC introduction
Section 21: Flexible static memory controller (FSMC) on page 488
Section 22: Secure digital input/output interface (SDIO) on page 541
Doc ID 13902 Rev 12
Changes
added
Clock interrupt register (RCC_CIR)
Clock control register (RCC_CR)
modified
Figure 21: External interrupt/event GPIO
263:
added
Figure 52: Advanced-control timer block
324.
modified. Section 17: Basic timers (TIM6&TIM7)
Section 18.2: RTC main features on page
modified.
Revision history
updated
updated
updated
updated
updated
updated (see
values).
Section
updated
189:
mapping)
updated
205:
updated,
added, etc.)
added.
280:
347:
updated. Table 86: TIMx Internal
added.
added.
9.3.2,
updated, notes
Table 70:
added.
465.
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