Reference Arm Documentation; Swj Debug Port (Serial Wire And Jtag); Mechanism To Select The Jtag-Dp Or The Sw-Dp; Figure 360. Swj Debug Port - ST STM32F101xx Reference Manual

Advanced arm-based 32-bit mcus

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Debug support (DBG)

Reference ARM documentation

Cortex™-M3 r1p1 Technical Reference Manual (TRM)

It is available from:

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337e/DDI0337E_cortex_m3_r1p1_trm.pdf

ARM Debug Interface V5

ARM CoreSight Design Kit revision r1p1 Technical Reference Manual

The STM32F10xxx core integrates the Serial Wire / JTAG Debug Port (SWJ-DP). It is an

ARM standard CoreSight debug port that combines a JTAG-DP (5-pin) interface and a SW-

DP (2-pin) interface.

The JTAG Debug Port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHP-

The Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the

AHP-AP port.

In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG

pins of the JTAG-DP.

TDO. This means that the asynchronous trace can only be used with SW-DP, not JTAG-DP.

By default, the JTAG-Debug Port is active.

shows that the asynchronous TRACE output (TRACESWO) is multiplexed with

Doc ID 13902 Rev 12

(asynchronous trace)