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Revision history
Table 232. Document revision history (continued)
Date
Revision
10
04-Dec-2009
continued
23-Apr-2010
11
1090/1096
TXFELVL bit description modified in
(OTG_FS_GAHBCFG).
NPTXFE bit description modified in
NPTXFEM bit description modified in
(OTG_FS_GINTMSK).
Figure 311: Transmit FIFO write task
Bit 22 is reserved in
OTG_FS interrupt mask register
Bit 29 description modified in
(OTG_FS_DIEPCTLx) (x = 1..3, where x =
Bits 21:20 no longer reserved in
(OTG_FS_HCCHARx) (x = 0..7, where x =
There are only 4 IN and OUT endpoints:
– Bit descriptions corrected in
(OTG_FS_DAINT).
– Bits 15:0 description corrected in
mask register: (OTG_FS_DIEPEMPMSK)
–
Table 204: OTG_FS register map and reset values
Note added to
Section 29.4: Ethernet functional description: SMI, MII and RMII on
page
942.
Note added to
Unicast destination address filter
System consideration during power-down on page 972
Figure 325: ETH block diagram
descriptor Word0
and
TDES0: Transmit descriptor Word0: Transmit time stamp control and
status on page
967.
Ethernet MAC hash table high register (ETH_MACHTHR)
Description of bits 6:2 modified in
Peripheral register access specified in
XL-density devices added.
Flash access control register (FLASH_ACR)
External source (HSE bypass)
frequency modified.
HSEBYP bit description modified in
Section 8.3.1: Clock control register
SPI3_REMAP definition modified in
register
(AFIO_MAPR).
Figure 48: DMA block diagram in connectivity line devices
Figure 85: Center-aligned PWM waveforms (ARR=8)
OIS1N and OIS1 bit descriptions modified in
(TIMx_CR2).
FSMC block diagram reinserted.
Figure 202: Synchronous multiplexed read mode - NOR, PSRAM (CRAM)
FSMC_ECCR2 and FSMC_ECCR3 reset value modified in
map.
Updated I2C Master mode
Notes modified in the bit 5 descriptions in
(OTG_FS_GINTSTS)
and
Transmission using DMA
Doc ID 13902 Rev 12
Changes
OTG_FS AHB configuration register
OTG_FS core interrupt register
OTG_FS interrupt mask register
modified.
OTG device endpoint-x control register
Endpoint_number).
OTG_FS Host channel-x characteristics register
Channel_number).
OTG_FS device all endpoints interrupt register
OTG_FS device IN endpoint FIFO empty interrupt
(there are only 4 endpoints).
and
modified. CIC bit description modified in
Ethernet DMA bus mode register
Section 29.8: Ethernet register
inserted.
and
External source (HSE bypass)
Section 7.3.1: Clock control register (RCC_CR)
(RCC_CR).
Section 9.4.2: AF remap and debug I/O configuration
Section 14.4.2: TIM1&TIM8 control register 2
Slave address transmission on page 733
OTG_FS core interrupt register
OTG_FS interrupt mask register
updated.
(OTG_FS_GINTSTS).
(OTG_FS_GINTMSK).
corrected
Multicast destination address
updated.
TDES0: Transmit
description clarified.
(ETH_DMABMR).
descriptions.
: maximum HSE
modified.
modified.
modified.
Table 135: FSMC register
(OTG_FS_GINTMSK).
RM0008
filter.
and
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