Figure 311. Transmit Fifo Write Task - ST STM32F101xx Reference Manual

Advanced arm-based 32-bit mcus
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USB on-the-go full-speed (OTG_FS)
1.
When an STALL, TXERR, BBERR or DTERR interrupt in OTG_FS_HCINTx is received
for an IN or OUT channel. The application must be able to receive other interrupts
(DTERR, Nak, Data, TXERR) for the same channel before receiving the halt.
2.
When a DISCINT (Disconnect Device) interrupt in OTG_FS_GINTSTS is received.
(The application is expected to disable all enabled channels).
3.
When the application aborts a transfer before normal completion.
Operational model
The application must initialize a channel before communicating to the connected device.
This section explains the sequence of operation to be performed for different types of USB
transactions.
Writing the transmit FIFO
The OTG_FS host automatically writes an entry (OUT request) to the periodic/non-
periodic request queue, along with the last Word write of a packet. The application must
ensure that at least one free space is available in the periodic/non-periodic request
queue before starting to write to the transmit FIFO. The application must always write to
the transmit FIFO in Words. If the packet size is non-Word aligned, the application must
use padding. The OTG_FS host determines the actual packet size based on the
programmed maximum packet size and transfer size.

Figure 311. Transmit FIFO write task

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Read GNPTXSTS/HPTXFSIZ
registers for available FIFO
and queue spaces
Wait for NPTXFE/PTXFE
interrupt in
OTG_FS_GINTSTS
MPS: Maximum packet size
LPS: Last packet size
Doc ID 13902 Rev 12
Start
1 MPS or
LPS FIFO space
No
available?
Yes
Write 1 packet
data to
transmit FIFO
More packets
to send?
No
Done
RM0008
Yes
ai15673b

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