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RM0008
31.6.3
Cortex-M3 TAP
The TAP of the ARM Cortex-M3 integrates a JTAG ID code. This ID code is the ARM default
one and has not been modified. This code is only accessible by the JTAG Debug Port.
This code is 0x3BA00477 (corresponds to Cortex-M3 r1p1-01rel0, see
Reference ARM
Only the DEV_ID(11:0) should be used for identification by the debugger/programmer tools.
31.6.4
Cortex-M3 JEDEC-106 ID code
The ARM Cortex-M3 integrates a JEDEC-106 ID code. It is located in the 4KB ROM table
mapped on the internal PPB bus at address 0xE00FF000_0xE00FFFFF.
This code is accessible by the JTAG Debug Port (4 to 5 pins) or by the SW Debug Port (two
pins) or by the user software.
31.7
JTAG debug port
A standard JTAG state machine is implemented with a 4-bit instruction register (IR) and five
data registers (for full details, refer to the Cortex-M3 r1p1 Technical Reference Manual
(TRM), for references, please see
Table 217. JTAG debug port data registers
IR(3:0)
1111
1110
1010
documentation).
Data register
BYPASS
[1 bit]
IDCODE
ID CODE
[32 bits]
0x3BA00477 (ARM Cortex-M3 r1p1-01rel0 ID Code)
Debug port access register
This initiates a debug port and allows access to a debug port register.
– When transferring data IN:
Bits 34:3 = DATA[31:0] = 32-bit data to transfer for a write request
Bits 2:1 = A[3:2] = 2-bit address of a debug port register.
Bit 0 = RnW = Read request (1) or write request (0).
DPACC
– When transferring data OUT:
[35 bits]
Bits 34:3 = DATA[31:0] = 32-bit data which is read following a read
request
Bits 2:0 = ACK[2:0] = 3-bit Acknowledge:
010 = OK/FAULT
001 = WAIT
OTHER = reserved
Refer to
Doc ID 13902 Rev 12
Section 31.2: Reference ARM
Table 218
for a description of the A(3:2) bits
Debug support (DBG)
Section 31.2:
documentation).
Details
1057/1096
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