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RM0008
Table 232. Document revision history (continued)
Date
Revision
26-Sep-2008
6
This reference manual also applies to low-density STM32F101xx, STM32F102xx and
STM32F103xx devices, and to medium-density STM32F102xx devices. In all sections,
definitions of low-density and medium-density devices updated.
Section 2.3: Peripheral availability on page 46
Section 3.3.3: Embedded Flash memory on page 54
backup domain on page 67
(x=A..G) on page 166
modified. Note added in
Note removed from bits 18:0 description in
page
203.
Section 14.2: TIM1&TIM8 main features on page 281
features on page 348
updated. In
TS=000.
FSMC_CLK signal direction corrected in
"Feedback clock" paragraph removed from
page
498.
In
Section 21.5.6: NOR/PSRAM controller registers on page
WAITEN bit default value after reset is 1, bits [5:6] definition modified, , FACCEN default
value after reset specified. NWE signal behavior corrected in
multiplexed write mode - PSRAM (CRAM) on page
support COSMO RAM and OneNAND devices, and it does not support the asynchronous
wait feature. SRAM and ROM 32 memory data size removed from
Flash/PSRAM supported memories and transactions on page
Data latency versus NOR Flash latency on page 515
in
SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4) on page
Section 21.6.3: Timing diagrams for NAND and PC Card on page 529
of PWID bits modified in
page
535.
Section 21.6.6: Error correction code computation ECC (NAND Flash) on
page 532
modified.
Interrupt Mapper definition modified in
page
601. USB register and memory base addresses modified in
registers on page
613.
Section 26.3.8: Packet error checking on page 745
Section : Start bit detection on page 768
register (USART_SR) on page
"RAM size register" section removed from
page
1045. Bit definitions updated in
(FSMC_SR2..4) on page
Small text changes.
Doc ID 13902 Rev 12
Changes
added.
modified. Reset value of
Section 9.4: AFIO registers on page
Section 10.3.6: Pending register (EXTI_PR) on
Section 15.3.15: Timer synchronization on page
Figure 185: FSMC block diagram on page
Section 21.5.3: General timing rules on
Section 21.6.8: NAND Flash/PC Card controller registers on
Section 23.3.1: Description of USB blocks on
added. PE bit description specified in
792.
Section 30: Device electronic signature on
FIFO status and interrupt register 2..4
536.
Revision history
updated.
Section 5.1.2: Battery
Port input data register (GPIOx_IDR)
and
Section 15.2: TIMx main
521: reset value modified,
Figure 203: Synchronous
519. The FSMC interface does not
Table 107: NOR
497.
modified. Bits 19:16 bits are reserved
modified.Definition
Section 23.5: USB
modified.
176.
378,
490.
525.
Status
1085/1096
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