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Debug support (DBG)
31.17.10 Example of configuration
●
Set the bit TRCENA in the Debug Exception and Monitor Control Register (DEMCR)
●
Write the TPIU Current Port Size Register to the desired value (default is 0x1 for a 1-bit
port size)
●
Write TPIU Formatter and Flush Control Register to 0x102 (default value)
●
Write the TPIU Select Pin Protocol to select the sync or async mode. Example: 0x2 for
async NRZ mode (UART like)
●
Write the DBGMCU control register to 0x20 (bit IO_TRACEN) to assign TRACE IOs for
async mode. A TPIU Sync packet is emitted at this time (FF_FF_FF_7F)
●
Configure the ITM and write the ITM Stimulus register to output a value
31.18
DBG register map
The following table summarizes the Debug registers.
Table 231. DBG register map and reset values
Addr.
Register
DBGMCU_
IDCODE
(1)
Reset value
X X X X X X X X X X X X X X X X
DBGMCU_CR
Reset value
1. The reset value is product dependent. For more information, refer to
1078/1096
REV_ID
Reserved
0
0
Doc ID 13902 Rev 12
Reserved
X X X X X X X X X X X X
0
0
0
0
0
0
0
0
0
Section 31.6.1: MCU device ID
RM0008
DEV_ID
0
0
0
0
0
0
0
code.
0
0
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