Ethernet Interrupts; Figure 357. Interrupt Scheme - ST STM32F101xx Reference Manual

Advanced arm-based 32-bit mcus

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interrupt. Even then, a new interrupt is generated, due to the active or pending Receive

buffer unavailable interrupt.

Ethernet interrupts

The Ethernet controller has two interrupt vectors: one dedicated to normal Ethernet

operations and the other, used only for the Ethernet wakeup event (with wakeup frame or

Magic Packet detection) when it is mapped on EXTI lIne19.

The first Ethernet vector is reserved for interrupts generated by the MAC and the DMA as

listed in the

The second vector is reserved for interrupts generated by the PMT on wakeup events. The

mapping of a wakeup event on EXTI line19 causes the STM32F107xx to exit the low power

mode, and generates an interrupt.

When an Ethernet wakeup event mapped on EXTI Line19 occurs and the MAC PMT

interrupt is enabled and the EXTI Line19 interrupt, with detection on rising edge, is also

enabled, both interrupts are generated.

A watchdog timer (see ETH_DMARSWTR register) is given for flexible control of the RS bit

(ETH_DMASR register). When this watchdog timer is programmed with a non-zero value, it

gets activated as soon as the RxDMA completes a transfer of a received frame to system

memory without asserting the Receive Status because it is not enabled in the corresponding

Receive descriptor (RDES1[31]). When this timer runs out as per the programmed value,

the RS bit is set and the interrupt is asserted if the corresponding RIE is enabled in the

Ethernet (ETH): media access control (MAC) with DMA controller

MAC interrupts

Doc ID 13902 Rev 12

DMA interrupts