Tim9 And Tim12 Registers; Tim9/12 Control Register 1 (Timx_Cr1) - ST STM32F101xx Reference Manual

RM0008
16.5

TIM9 and TIM12 registers

Refer to
16.5.1

TIM9/12 control register 1 (TIMx_CR1)

Address offset: 0x00
Reset value: 0x0000
15 14 13
Reserved
Bits 15:10 Reserved, always read as 0
Bits 9:8 CKD: Clock division
Bit 7 ARPE: Auto-reload preload enable
Bits 6:4 Reserved
Bit 3 OPM: One-pulse mode
Bit 2 URS: Update request source
Bit 1 UDIS: Update disable
Bit 0 CEN: Counter enable
CEN is cleared automatically in one-pulse mode, when an update event occurs.
Section 1.1 for a list of abbreviations used in register descriptions.
12 11 10 9
CKD[1:0]
rw
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
sampling clock used by the digital filters (TIx),
00: t = t
DTS CK_INT
01: t = 2 × t
DTS CK_INT
10: t = 4 × t
DTS CK_INT
11: Reserved
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
0: Counter is not stopped on the update event
1: Counter stops counting on the next update event (clearing the CEN bit).
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generates an update interrupt if enabled:
– Counter overflow
– Setting the UG bit
1: Only counter overflow generates an update interrupt if enabled.
This bit is set and cleared by software to enable/disable update event (UEV) generation.
0: UEV enabled. An UEV is generated by one of the following events:
– Counter overflow
– Setting the UG bit
Buffered registers are then loaded with their preload values.
1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC,
CCRx). The counter and the prescaler are reinitialized if the UG bit is set.
0: Counter disabled
1: Counter enabled
Doc ID 13902 Rev 12
General-purpose timers (TIM9 to TIM14)
8 7 6 5
ARPE
reserved
rw rw
4 3 2 1
OPM URS UDIS
rw rw rw
429/1096
0
CEN
rw