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RM0008
Bit 3 TJTS: Transmit jabber timeout status
This bit indicates that the transmit jabber timer expired, meaning that the transmitter had been
excessively active. The transmission process is aborted and placed in the Stopped state. This
causes the transmit jabber timeout TDES0[14] flag to be asserted.
Bit 2 TBUS: Transmit buffer unavailable status
This bit indicates that the next descriptor in the transmit list is owned by the host and cannot be
acquired by the DMA. Transmission is suspended. Bits [22:20] explain the transmit process
state transitions. To resume processing transmit descriptors, the host should change the
ownership of the bit of the descriptor and then issue a Transmit Poll Demand command.
Bit 1 TPSS: Transmit process stopped status
This bit is set when the transmission is stopped.
Bit 0 TS: Transmit status
This bit indicates that frame transmission is finished and TDES1[31] is set in the first descriptor.
Ethernet DMA operation mode register (ETH_DMAOMR)
Address offset: 0x1018
Reset value: 0x0000 0000
The operation mode register establishes the Transmit and Receive operating modes and
commands. The ETH_DMAOMR register should be the last CSR to be written as part of
DMA initialization.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
rw rw rw
Bits 31:27 Reserved
Bit 26 DTCEFD: Dropping of TCP/IP checksum error frames disable
When this bit is set, the core does not drop frames that only have errors detected by the
receive checksum offload engine. Such frames do not have any errors (including FCS error) in
the Ethernet frame received by the MAC but have errors in the encapsulated payload only.
When this bit is cleared, all error frames are dropped if the FEF bit is reset.
Bit 25 RSF: Receive store and forward
When this bit is set, a frame is read from the Rx FIFO after the complete frame has been
written to it, ignoring RTC bits. When this bit is cleared, the Rx FIFO operates in Cut-through
mode, subject to the threshold specified by the RTC bits.
Bit 24 DFRF: Disable flushing of received frames
When this bit is set, the RxDMA does not flush any frames due to the unavailability of receive
descriptors/buffers as it does normally when this bit is cleared. (See
suspended on page
Bits 23:22 Reserved
Ethernet (ETH): media access control (MAC) with DMA controller
Reserved
rw
rs
rw rw rw rw
994)
Doc ID 13902 Rev 12
9
8
7
6
5
Reserved
rw rw
Receive process
4
3
2
1
0
rw rw rw rw
1035/1096
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