ST STM32F101xx Reference Manual page 1041

Advanced arm-based 32-bit mcus

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Ethernet DMA current host receive descriptor register (ETH_DMACHRDR)

Address offset: 0x104C

Reset value: 0x0000 0000

The Current host receive descriptor register points to the start address of the current receive

descriptor read by the DMA.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Bits 31:0 HRDAP: Host receive descriptor address pointer

Cleared on Reset. Pointer updated by DMA during operation.

Ethernet DMA current host transmit buffer address register

(ETH_DMACHTBAR)

Address offset: 0x1050

Reset value: 0x0000 0000

The Current host transmit buffer address register points to the current transmit buffer

address being read by the DMA.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Bits 31:0 HTBAP: Host transmit buffer address pointer

Cleared on reset. Pointer updated by DMA during operation.

Ethernet DMA current host receive buffer address register

(ETH_DMACHRBAR)

Address offset: 0x1054

Reset value: 0x0000 0000

The current host receive buffer address register points to the current receive buffer address

being read by the DMA.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Bits 31:0 HRBAP: Host receive buffer address pointer

Cleared on reset. Pointer updated by DMA during operation.

Ethernet (ETH): media access control (MAC) with DMA controller

Doc ID 13902 Rev 12