Tim9/12 Status Register (Timx_Sr) - ST STM32F101xx Reference Manual

Advanced arm-based 32-bit mcus

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TIM9/12 status register (TIMx_SR)

Address offset: 0x10

Reset value: 0x0000

Reserved, always read as 0.

Bit 10 CC2OF: Capture/compare 2 overcapture flag

refer to CC1OF description

Bit 9 CC1OF: Capture/Compare 1 overcapture flag

This flag is set by hardware only when the corresponding channel is configured in input

capture mode. It is cleared by software by writing it to '0'.

0: No overcapture has been detected.

1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was

Reserved, always read as 0.

Bit 6 TIF: Trigger interrupt flag

This flag is set by hardware on trigger event (active edge detected on TRGI input when the

slave mode controller is enabled in all modes but gated mode. It is set when the counter

starts or stops when gated mode is selected. It is cleared by software.

0: No trigger event occurred.

1: Trigger interrupt pending.

Reserved, always read as 0

Bit 2 CC2IF: Capture/Compare 2 interrupt flag

refer to CC1IF description

Bit 1 CC1IF: Capture/compare 1 interrupt flag

If channel CC1 is configured as output:

This flag is set by hardware when the counter matches the compare value. It is cleared by

0: No match.

1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.

When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF

bit goes high on the counter overflow.

If channel CC1 is configured as input:

This bit is set by hardware on a capture. It is cleared by software or by reading the

TIMx_CCR1 register.

0: No input capture occurred.

1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected

on IC1 which matches the selected polarity).

Doc ID 13902 Rev 12

General-purpose timers (TIM9 to TIM14)