Table 96. Min/Max Iwdg Timeout Period At 740 Khz (Lsi) - ST STM32F101xx Reference Manual

Revision history
Table 232. Document revision history (continued)
Date Revision
19-Oct-2007 1
continued continued
1080/1096
Figure 114: Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6
Figure 129: Output compare mode, toggle on OC1.
Section 15.4.1: TIMx control register 1
Bit 8 and Bit 9 added to
it 15 and Bit 16 added to
page 747 added.
Stop and Standby modified in
Table 13: Sleep-on-exit modified.
HSITRIM[4:0] bit description modified in
Note modified in MCO description in
(RCC_CFGR). RCC_CR row modified in
Bits 15:0 description modified in
(x=A..G). Embedded boot loader on page 61
Figure 13, Figure 15, Figure
Section 3.3.3: Embedded Flash memory on page 54
REV_ID bit description added to
Reset value modified in
description modified.
Section 9.1.1 on page 156
on page 165. Wakeup latency description modified in
Clock control register (RCC_CR)
Note added in ASOS and ASOE bit descriptions in
Section 31.16.2: Debug support for timers, watchdog, bxCAN and I2C
DBG register map and reset values
Section 23.5.3: Buffer descriptor table
Center-aligned mode (up/down counting) on page 289
counting) on page 356 updated.
Figure 85: Center-aligned PWM waveforms (ARR=8) on page 304
Center-aligned PWM waveforms (ARR=8) on page 370
RSTCAL description modified in
Note changed below Table 96: Min/max IWDG timeout period at 740 kHz
added below Figure 8: Clock
ADC conversion time modified in
Auto-injection on page 212
Note added in Section 11.9.9: Combined injected simultaneous +
to Section 9.3.2: Using OSC_IN/OSC_OUT pins as GPIO ports
changes. Internal LSI RC frequency changed from 32 to 40 kHz.
timeout period at 740 kHz (LSI)
Memory map and Table 5: Flash module organization (medium-density
Information block organization modified in
External event that trigger ADC conversion is EXTI line instead of external interrupt (see
Section 11: Analog-to-digital converter
Appendix A: Important notes on page 500
Doc ID 13902 Rev 12
Changes
(TIMx_CR1).
Section 6.4.2: RTC clock calibration register
DBGMCU_CR on page
Table 11: Low-power mode
Debug mode on page 75
Section 7.3.1: Clock control register
Section 7.3.2: Clock configuration register
RCC register map and reset values on page
Section 9.2.6: Port bit reset register (GPIOx_BRR)
added.
16, Figure 17 and Figure 18
DBGMCU_IDCODE on page
Clock control register (RCC_CR) on page 96
modified. Bit definitions modified in
reset value modified.
updated.
clarified.
Section 11.12.3: ADC control register 2
tree.
Section 11.2: ADC main
updated.
updated. Option byte addresses corrected in
Section 3.3.3: Embedded Flash
(ADC)).
added.
modified. CKD definition modified in
(BKP_RTCCR).
1069. Section 26.5: I2C debug mode on
summary.
modified.
modified.
modified.
1055.
and HSITRIM[4:0]
Section 9.2: GPIO registers
Table 14: Stop mode.
6.4.2 on page 81.
modified.
and Center-aligned mode (up/down
and Figure 131:
modified.
(ADC_CR2).
features.
interleaved. Note added
PD0/PD1. Small text
Table 96: Min/max IWDG
devices).
RM0008
and
(RCC_CR).
119.
Table 231:
(LSI). Note
Figure 2:
memory.