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Ethernet (ETH): media access control (MAC) with DMA controller
Bit 21 TSF: Transmit store and forward
When this bit is set, transmission starts when a full frame resides in the Transmit FIFO. When
this bit is set, the TTC values specified by the ETH_DMAOMR register bits [16:14] are ignored.
When this bit is cleared, the TTC values specified by the ETH_DMAOMR register bits [16:14]
are taken into account.
This bit should be changed only when transmission is stopped.
Bit 20 FTF: Flush transmit FIFO
When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all
data in the Tx FIFO are lost/flushed. This bit is cleared internally when the flushing operation is
complete. The Operation mode register should not be written to until this bit is cleared.
Bits 19:17 Reserved
Bits 16:14 TTC: Transmit threshold control
These three bits control the threshold level of the Transmit FIFO. Transmission starts when the
frame size within the Transmit FIFO is larger than the threshold. In addition, full frames with a
length less than the threshold are also transmitted. These bits are used only when the TSF bit
(Bit 21) is cleared.
Bit 13 ST: Start/stop transmission
When this bit is set, transmission is placed in the Running state, and the DMA checks the
transmit list at the current position for a frame to be transmitted. Descriptor acquisition is
attempted either from the current position in the list, which is the transmit list base address set
by the ETH_DMATDLAR register, or from the position retained when transmission was
stopped previously. If the current descriptor is not owned by the DMA, transmission enters the
Suspended state and the transmit buffer unavailable bit (ETH_DMASR [2]) is set. The Start
Transmission command is effective only when transmission is stopped. If the command is
issued before setting the DMA ETH_DMATDLAR register, the DMA behavior is unpredictable.
When this bit is cleared, the transmission process is placed in the Stopped state after
completing the transmission of the current frame. The next descriptor position in the transmit
list is saved, and becomes the current position when transmission is restarted. The Stop
Transmission command is effective only when the transmission of the current frame is
complete or when the transmission is in the Suspended state.
Bits 12:8 Reserved
Bit 7 FEF: Forward error frames
When this bit is set, all frames except runt error frames are forwarded to the DMA.
When this bit is cleared, the Rx FIFO drops frames with error status (CRC error, collision error,
giant frame, watchdog timeout, overflow). However, if the frame's start byte (write) pointer is
already transferred to the read controller side (in Threshold mode), then the frames are not
dropped. The Rx FIFO drops the error frames if that frame's start byte is not transferred
(output) on the ARI bus.
1036/1096
000: 64
001: 128
010: 192
011: 256
100: 40
101: 32
110: 24
111: 16
Doc ID 13902 Rev 12
RM0008
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