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RM0008
Table 232. Document revision history (continued)
Date
Revision
20-Nov-2007
2
Figure 27.3.1: USART block diagramUSART character description
Procedure modified in
Character reception on page
In
Section 27.3.4: Fractional baud rate
– Equation legend modified
–
Table 191: Error calculation for programmed baud rates
– Note added
Small text changes. In
CAN bit timing register (CAN_BTR) on page
Flash memory organization corrected,
density devices)
modified in
Note added below
Figure 4: Power supply overview
RTCSEL[1:0] bit description modified in
Names of bits [0:2] corrected for RCC_APB1RSTR and RCC_APB1ENR in
register map and reset
values.
Impedance value specified in
In
Section 25.5.1: SPI control register 1 (SPI_CR1) (not used in I2S
description corrected.
Prescaler buffer behavior specified when an update event occurs (see
on page
351,
Downcounting mode on page 354
counting)).
AWDCH[4:0] modified in
[26:24] are reserved in
Section 11.12.4: ADC sample time register 1
CAN_BTR bit 8 is reserved in
master control register (CAN_MCR) on page 650
V
range corrected in
REF+
page
66.
Start condition on page 733
remapping. Note added in
In
Section 9.4.2: AF remap and debug I/O configuration register
definition modified for USART2_REMAP = 0. In
configuration register 1
(AFIO_EXTICR1), bit definition modified for SPI1_REMAP = 0. In
Table 230: Important TPIU
TRACE port size setting corrected in
Figure
13,
Figure
15,
Figure
structure of a five-volt tolerant I/O port bit
Table 9.3.1: Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15 on page 169
added.
Bit descriptions modified in
JTAG ID code corrected in
Modified:
Section 20.2: WWDG main
Section 6.3.1: Tamper
detection,
functional
description,
Controlling the
domain,
Section 8.2:
Introduction.
ASOE bit description modified in
(BKP_RTCCR).
Doc ID 13902 Rev 12
Changes
generation:
Table 5: Flash module organization (medium-
Section 3.3.3: Embedded Flash
Backup domain control register
A.4: Voltage glitch on ADC input 0 on page
and
Section 11.12.2: ADC control register 1 (ADC_CR1)
Table 180: bxCAN register map and reset
Table 65: ADC pins
and in
updated. Note removed in
Table 43: TIM4 alternate function
Section 9.4.3: External interrupt
registers, at 0xE0040004, bit2 set is not supported.
TPUI TRACE pin assignment on page
16,
Figure 17
and
Figure 18
added.
Section 18.4.5
and
Section
Section 31.6.2: Boundary scan TAP on page 1056
features,
Section 6.2: BKP main
Section 6.3.2: RTC
downcounter:,
Section 6.4.2: RTC clock calibration register
Revision history
modified.
769.
modified
659, bit 15 is reserved.
memory.
in
Section 5.1: Power
(RCC_BDCR).
500.
mode), BR[2:0]
Upcounting mode
Center-aligned mode (up/down
(ADC_SMPR1).
values.
corrected.
On 100-pin and 144-pin packages on
Table 34: CAN1 alternate function
remapping.
(AFIO_MAPR), bit
modified.
Figure 14: Basic
18.4.6.
features,
calibration,
Section 23.3: USB
Section 5.1.2: Battery backup
supplies.
Table 18: RCC
and bits
CAN
1073.
.
1081/1096
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