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Revision history
Table 232. Document revision history (continued)
Date
Revision
23-Dec-2008
7
1086/1096
Memory map figure removed from reference manual.
page 47
modified.
Section 3.4: Boot configuration on page 60
mode on page 71
modified.
event management on page 198
Section 7.3: RCC registers on page 96
page 263
updated.
Section 13.3.5: Error management
connectivity line devices on page 264
data alignment and endians on page 268
Bit definition modified in
(DMA_CPARx) (x = 1..7), where x = channel number) on page 277
DMA channel x memory address register (DMA_CMARx) (x = 1..7), where x = channel
number) on page
277.
Note added below
Figure 82: PWM input mode timing
timing.
FSMC_NWAIT signal direction corrected in
Value to set modified for bit 6 in
FSMC_BCRx bit fields
and
Flash,
Table 130: 16-bit NAND Flash
INTR signals separated in
definition in
PC Card/NAND Flash control registers 2..4 (FSMC_PCR2..4) on page
Bit definitions updated in
page
536. Note modified in ADDHLD and ADDSET bit definitions in
chip-select timing registers 1..4 (FSMC_BTR1..4) on page
Card/NAND Flash control registers 2..4 (FSMC_PCR2..4) on page
MEMWAIT[15:8] bit definition modified in
(FSMC_PMEM2..4) on page
ATTWAIT[15:8] bit definition modified in
(FSMC_PATT2..4) on page
Section 21.6.5: NAND Flash pre-wait functionality on page 531
NAND/PC Card controller timing for common memory access
Note added below
Table 99: NOR/PSRAM bank selection on page
32-bit external memory access removed from
page 493
and note added.
Caution:
added to
Section 21.6.1: External memory interface
NIOS16 description modified in
Register description modified in
(FSMC_PATT2..4) on page
Resetting the password on page 563
write_data signal modified in
memory
access.
bxCAN main features on page 630
Section 26.3.8: Packet error checking on page 745
Section 31.6.3: Cortex-M3 TAP
DBG_TIMx_STOP positions modified in
Small text changes.
Doc ID 13902 Rev 12
Changes
Section 6.3.2: RTC calibration on page 80
updated.
updated.
modified.
Figure 48: DMA block diagram in
modified.
Section 13.3.4: Programmable data width,
added.
Section 13.4.5: DMA channel x peripheral address register
Figure 185: FSMC block diagram on page
Table 113: FSMC_BCRx bit
Table 122: FSMC_BCRx bit
and
Table 131: 16-bit PC Card
Table 131: 16-bit PC
Card. Note added in PWAITEN bit
FIFO status and interrupt register 2..4 (FSMC_SR2..4) on
Common memory space timing register 2..4
537.
Attribute memory space timing registers 2..4
538.
Table 100: External memory address on
Table 131: 16-bit PC Card on page
Attribute memory space timing registers 2..4
538.
step 2 corrected.
Figure 204: NAND/PC Card controller timing for common
modified.
modified.
DBGMCU_CR on page
Section 3.1: System architecture on
modified.
Exiting Sleep
updated.
Section 13.2: DMA main features on
and
Section 13.4.6:
and
Figure 128: PWM input mode
fields,
Table 116:
fields.
Table 129: 8-bit NAND
modified. NWAIT and
SRAM/NOR-Flash
523. Bit 8 is reserved in
535.
modified.
modified.
492.
signals.
528.
modified.
1069.
RM0008
Wakeup
490.
535.
PC
Figure 204:
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