Table 123. Fsmc_Btrx Bit Fields - ST STM32F101xx Reference Manual

Flexible static memory controller (FSMC)
Table 122. FSMC_BCRx bit fields
Bit No.
31-16
15
14
13-10
9
8
7
6
5-4
3-2
1
0

Table 123. FSMC_BTRx bit fields

Bit No.
31-20
19-16
15-8
7-4
3-0
WAIT management in asynchronous accesses
If the asynchronous memory asserts a WAIT signal to advise that it's not yet ready to accept
or to provide data, the ASYNCWAIT bit has to be set in FSMC_BCRx register.
If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access
phase (Data setup phase) programmed by the DATAST bits, is extended until WAIT
becomes inactive. Unlike the data setup phase, the first access phases (Address setup and
Address hold phases), programmed by the ADDSET and ADDHLD bits, are not WAIT
sensitive and so they are not prolonged.
The data phase must be programmed so that WAIT can be detected 4 HCLK cycles before
the data sampling. The following cases must be considered:
512/1096
Bit name
0x0000
ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
EXTMOD 0x0
0x0
WAITPOL Meaningful only if bit 15 is 1
BURSTEN 0x0
-
FACCEN 0x1
MWID As needed
MTYP 0x2 (NOR)
MUXEN 0x1
MBKEN 0x1
Bit name
0x0000
Duration of the last phase of the access (BUSTURN+1 HCLK)
BUSTURN
Duration of the second access phase (DATAST+3 HCLK cycles for
DATAST read accesses and DATAST+1 HCLK cycles for write accesses).
This value cannot be 0 (minimum is 1)
Duration of the middle phase of the access (ADDHLD+1 HCLK
ADDHLD
cycles).This value cannot be 0 (minimum is 1).
ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles).
Doc ID 13902 Rev 12
Value to set
Value to set
RM0008