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Ethernet (ETH): media access control (MAC) with DMA controller
Ethernet PTP time stamp low register (ETH_PTPTSLR)
Address offset: 0x070C
Reset value: 0x0000 0000
This register contains the least significant (lower) 32 time bits. This read-only register
contains the subsecond system time value.
31
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
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Bit 31 STPNS: System time positive or negative sign
Bits 30:0 STSS: System time subseconds
Ethernet PTP time stamp high update register (ETH_PTPTSHUR)
Address offset: 0x0710
Reset value: 0x0000 0000
This register contains the most significant (higher) 32 bits of the time to be written to, added
to, or subtracted from the System Time value. The Time stamp high update register, along
with the Time stamp update low register, initializes or updates the system time maintained
by the MAC. You have to write both of these registers before setting the TSSTI or TSSTU
bits in the Time stamp control register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 TSUS: Time stamp update second
The value in this field indicates the time, in seconds, to be initialized or added to the system
time.
1026/1096
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This bit indicates a positive or negative time value. When set, the bit indicates that time
representation is negative. When cleared, it indicates that time representation is positive.
Because the system time should always be positive, this bit is normally zero.
The value in this field has the subsecond time representation, with 0.46 ns accuracy.
Doc ID 13902 Rev 12
STSS
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TSUS
9
8
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5
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9
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7
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5
RM0008
4
3
2
1
0
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4
3
2
1
0
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