Table 83. Output Control Bits For Complementary Ocx And Ocxn Channels With - ST STM32F101xx Reference Manual

Revision history
Table 232. Document revision history (continued)
Date Revision
08-Feb-2008 3
4
continued
22-May-2008
on next
page
1082/1096
Figure 4: Power supply overview on page 66
Section 7.1.2: Power reset on page 88
Section 7.2: Clocks on page 89
Definition of Bits 26:24 modified in
register (AFIO_MAPR) on page
bits corrected in
AFIO_EVCR
Number of maskable interrupt channels modified in
interrupt controller (NVIC) on page 189
Section 13.3.6: Interrupts on page 269
Examples modified in Figure 91: 6-step generation, COM example (OSSR=1) on
page 310.
Table 83: Output control bits for complementary OCx and OCxN channels with break
feature on page 337 modified.
Register names modified in
Small text change in Section 26.3.3: I2C master mode on page
Bits 5:0 frequency description modified in
page 749.
Section 23.3.1: Description of USB blocks on page 601
Section 25.3.4: Configuring the SPI for Simplex communication on page 683
Section 25.3.6: CRC calculation on page 690
Note added in BUSY flag on page
Section 25.3.8: Disabling the SPI on page 693
Appendix A: Important notes, removed.
Reference manual updated to apply to devices containing up to 512 Kbytes of Flash
memory (High-density devices). Document restructured. Small text changes. Definitions of
Medium-density and High-density devices added to all sections.
In Section 3: Memory and bus architecture on page
– Figure 1: System architecture on page
Register boundary addresses on page 50
– Note and text added to
– SRAM size in Section 3.3.1: Embedded SRAM on page 53
– Section 3.3.3: Embedded Flash memory on page 54
number of pages, Reading the Flash
density devices) on page 56
– Prefetch buffer on/off specified in
bit_number definition modified in
Section 4: CRC calculation unit on page 62
on page 50 updated, Figure 2: Memory map on page 39
Section 7.3.6: AHB peripheral clock enable register (RCC_AHBENR) on page
Entering Stop mode on page 72
Updated in Section 6: Backup registers (BKP) on page
available storage size and
Section 6.4.2: RTC clock calibration register (BKP_RTCCR) on page
Doc ID 13902 Rev 12
Changes
modified.
modified.
modified.
Section 9.4.2: AF remap and debug I/O configuration
178.
Table 60: AFIO register map and reset values on page
.
added. Small text changes.
Section 24.9.4: CAN filter registers on page
Section 26.6.2: Control register 2 (I2C_CR2) on
modified.
692.
added.
47, Figure 2: Memory map on page
updated
AHB/APB bridges (APB) on page 49
memory, Table 6: Flash module organization (high-
added)
Reading the Flash memory
Section 3.3.2: Bit banding on page
added
specified.
Section 6.1: BKP introduction. ASOE definition modified in
Section 10.1: Nested vectored
667.
731.
modified.
47:
updated (Flash size, page size,
53.
(Table 3: Register boundary addresses
updated and CRCEN bit added to
79: number of backup registers and
81.
RM0008
187.
modified.
39, Table 3:
108).