Figure 359. Block Diagram Of Stm32F10Xxx-Level And; Cortex-M3-Level Debug Support - ST STM32F101xx Reference Manual

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Figure 359. Block diagram of STM32F10xxx-level and

JTMS/
SWDIO
JTDI
JTDO/
TRACESWO
NJTRST
JTCK/
SWCLK
Note: The debug features embedded in the Cortex-M3 core are a subset of the ARM CoreSight
Design Kit.
The ARM Cortex-M3 core provides integrated on-chip debug support. It is comprised of:
● SWJ-DP: Serial wire / JTAG debug port
●
AHP-AP: AHB access
● ITM: Instrumentation trace macrocell
●
FPB: Flash patch breakpoint
● DWT: Data watchpoint trigger
●
TPUI: Trace port unit interface (available on larger packages, where the corresponding
pins are mapped)
●
ETM: Embedded Trace Macrocell (available on larger packages, where the
corresponding pins are mapped)
It also includes debug features dedicated to the STM32F10xxx:
●
Flexible debug pinout assignment
●
MCU debug box (support for low-power modes, control over peripheral clocks, etc.)
Note: For further information on debug functionality supported by the ARM Cortex-M3 core, refer
to the Cortex-M3-r1p1 Technical Reference Manual and to the CoreSight Design Kit-r1p0
TRM (see

Cortex-M3-level debug support

STM32F10xxx debug support
Cortex-M3 debug support
Cortex-M3
Core
SWJ-DP
AHB-AP
Internal private
peripheral bus (PPB)
ort
p
Section 31.2: Reference ARM
Doc ID 13902 Rev 12
Bus matrix
Data
External private
peripheral bus (PPB)
Bridge
NVIC
DWT
FPB
ITM
documentation).
Debug support (DBG)
DCode
interface
System
interface
ETM
TRACESWO
Trace port
TRACECK
TPIU
TRACED[3:0]
DBGMCU
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