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Debug support (DBG)
31.4.1
SWJ debug port pins
Five pins are used as outputs from the STM32F10xxx for the SWJ-DP as alternate functions
of general-purpose IOs. These pins are available on all packages.
Table 215. SWJ debug port pins
SWJ-DP pin name
JTMS/SWDIO
JTCK/SWCLK
JTDI
JTDO/TRACESWO
NJTRST
31.4.2
Flexible SWJ-DP pin assignment
After RESET (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned
as dedicated pins immediately usable by the debugger host (note that the trace outputs are
not assigned except if explicitly programmed by the debugger host).
However, the STM32F10xxx MCU implements the
register (AFIO_MAPR)
releases the associated pins for General Purpose IOs usage. This register is mapped on an
APB bridge connected to the Cortex-M3 System Bus. Programming of this register is done
by the user software program and not the debugger host.
Three control bits allow the configuration of the SWJ-DP pin assignments. These bits are
reset by the System Reset.
●
AFIO_MAPR (@ 0x40010004 in the STM32F10xxx MCU)
–
–
Bit 26:24= SWJ_CFG[2:0]
Set and cleared by software.
These bits are used to configure the number of pins assigned to the SWJ debug port.
The goal is to release as much as possible the number of pins to be used as General
Purpose IOs if using a small size for the debug port.
The default state after reset is "000" (whole pins assigned for a full JTAG-DP
connection). Only one of the 3 bits can be set (it is forbidden to set more than one bit).
1052/1096
JTAG debug port
Type
JTAG Test Mode
I
Selection
I
JTAG Test Clock
I
JTAG Test Data Input
O
JTAG Test Data Output
I
JTAG Test nReset
register to disable some part or all of the SWJ-DP port and so
READ: APB - No Wait State
WRITE: APB - 1 Wait State if the write buffer of the AHB-APB bridge is full.
Doc ID 13902 Rev 12
Description
Type
IO
I
-
-
-
AF remap and debug I/O configuration
SW debug port
Debug assignment
Serial Wire Data
Input/Output
Serial Wire Clock
-
TRACESWO if async trace
is enabled
-
RM0008
Pin
assign
ment
PA13
PA14
PA15
PB3
PB4
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